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| motorola.com/semiconductors m68hc08 microcontrollers mc68hc908ql4/d rev. 0 mc68hc908ql4 data sheet mc68hc908ql3 mc68hc908ql2 9/2003
mc68hc908ql family data sheet motorola 3 motorola and the stylized m logo are registered trademarks of motorola, inc. digitaldna is a trademark of motorola, inc. this product incorporates superflash? technol ogy licensed from sst. ? motorola, inc., 2003 mc68hc908ql4 mc68hc908ql3 mc68hc908ql2 data sheet to provide the most up-to-date information, the revision of our documents on the world wide web will be the most current. your printed copy may be an earlier revision. to verify you have the latest information available, refer to: http://motorola.com/semiconductors/ the following revision history table summarizes changes contained in this document. for your convenience, the page number designators have been linked to the appropriate location. revision history data sheet mc68hc908ql family 4 revision history motorola revision history date revision level description page number(s) september, 2003 n/a initial release n/a mc68hc908ql family data sheet motorola list of sections 5 data sheet ? mc68hc908ql4 family list of sections section 1. general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 section 2. memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 section 3. analog-to-digital converter (adc) . . . . . . . . . . . . . . . . . . . 45 section 4. auto wakeup module (awu) . . . . . . . . . . . . . . . . . . . . . . . . 57 section 5. configuration regi ster (config) . . . . . . . . . . . . . . . . . . . . 63 section 6. computer operat ing properly (cop) . . . . . . . . . . . . . . . . . 67 section 7. central processor un it (cpu) . . . . . . . . . . . . . . . . . . . . . . . 71 section 8. external interrupt (irq) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 section 9. keyboard interrupt module (kbi) . . . . . . . . . . . . . . . . . . . . 91 section 10. low-voltage inhibit (lvi) . . . . . . . . . . . . . . . . . . . . . . . . . . 99 section 11. oscillator module (osc). . . . . . . . . . . . . . . . . . . . . . . . . . 103 section 12. input/output port s (ports) . . . . . . . . . . . . . . . . . . . . . . 113 section 13. system integrat ion module (sim) . . . . . . . . . . . . . . . . . . 121 section 14. slave lin interface controller (slic) . . . . . . . . . . . . . . . 139 section 15. timer interface module (tim) . . . . . . . . . . . . . . . . . . . . . . 187 section 16. development support . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 section 17. electrical specifications. . . . . . . . . . . . . . . . . . . . . . . . . . 225 section 18. ordering information and mechanical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239 list of sections data sheet mc68hc908ql family 6 list of sections motorola mc68hc908ql family data sheet motorola table of contents 7 data sheet ? mc68hc908ql4 family table of contents section 1. gener al description 1.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 1.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 1.3 mcu block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 1.4 pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 1.5 pin function priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 section 2. memory 2.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 2.2 unimplemented memory locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 2.3 reserved memory locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 2.4 input/output (i/o) section. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 2.5 random-access memory (ram) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 2.6 flash memory (flash) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 2.6.1 flash control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 2.6.2 flash page erase operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 2.6.3 flash mass erase operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 2.6.4 flash program operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 2.6.5 flash protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 2.6.6 flash block protect register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 2.6.7 wait mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 2.6.8 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 section 3. analog-to-di gital converter (adc) 3.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 3.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 3.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 3.3.1 adc port i/o pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 3.3.2 voltage conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 3.3.3 conversion time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 3.3.4 conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 3.3.5 accuracy and precision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 3.3.6 result justification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 3.4 monotonicity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 3.5 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 table of contents data sheet mc68hc908ql family 8 table of contents motorola 3.6 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 3.6.1 wait mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 3.6.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 3.7 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 3.7.1 adc analog power pin (v ddad ). . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 3.7.2 adc analog ground pin (v ssad ) . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 3.7.3 adc voltage reference high pin (v refh ) . . . . . . . . . . . . . . . . . . . . 51 3.7.4 adc voltage reference low pin (v refl ) . . . . . . . . . . . . . . . . . . . . 51 3.7.5 adc voltage in (v adin ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 3.8 i/o registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 3.8.1 adc status and control register . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 3.8.2 adc data register high and data regi ster low . . . . . . . . . . . . . . . 53 3.8.2.1 left justified mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 3.8.2.2 right justified mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 3.8.2.3 left justified signed data mode . . . . . . . . . . . . . . . . . . . . . . . . . . 54 3.8.2.4 eight bit truncation mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 3.8.3 adc clock register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 section 4. auto wakeup module (awu) 4.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 4.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 4.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 4.4 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 4.5 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 4.6 input/output registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 4.6.1 port a i/o register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 4.6.2 keyboard status and control register . . . . . . . . . . . . . . . . . . . . . . . 60 4.6.3 keyboard interrupt enable register . . . . . . . . . . . . . . . . . . . . . . . . . 61 section 5. configurat ion register (config) 5.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 5.2 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 section 6. computer o perating properly (cop) 6.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 6.2 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 6.3 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 6.3.1 busclkx4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 6.3.2 copctl write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 6.3.3 power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 6.3.4 internal reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 table of contents mc68hc908ql family data sheet motorola table of contents 9 6.3.5 reset vector fetch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 6.3.6 copd (cop disable) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 6.3.7 coprs (cop rate select) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 6.4 cop control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 6.5 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 6.6 monitor mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 6.7 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 6.7.1 wait mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 6.7.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 6.8 cop module during break mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 section 7. central processor un it (cpu) 7.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 7.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 7.3 cpu registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 7.3.1 accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 7.3.2 index register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 7.3.3 stack pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 7.3.4 program counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 7.3.5 condition code register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 7.4 arithmetic/logic unit (alu) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 7.5 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 7.5.1 wait mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 7.5.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 7.6 cpu during break interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 7.7 instruction set summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 7.8 opcode map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 section 8. external interrupt (irq) 8.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 8.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 8.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 8.4 irq pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 8.5 irq module during break interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 8.6 irq status and control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 table of contents data sheet mc68hc908ql family 10 table of contents motorola section 9. keyboard in terrupt module (kbi) 9.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 9.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 9.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 9.3.1 keyboard operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 9.3.2 keyboard initialization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 9.4 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 9.5 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 9.6 keyboard module during break interrupts . . . . . . . . . . . . . . . . . . . . . . . 95 9.7 input/output registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 9.7.1 keyboard status and control register . . . . . . . . . . . . . . . . . . . . . . . 96 9.7.2 keyboard interrupt enable register . . . . . . . . . . . . . . . . . . . . . . . . . 97 section 10. low-voltage inhibit (lvi) 10.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 10.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 10.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 10.3.1 polled lvi operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 10.3.2 forced reset operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 10.3.3 voltage hysteresis protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 10.3.4 lvi trip selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 10.4 lvi status register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 10.5 lvi interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 10.6 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 10.6.1 wait mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 10.6.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 section 11. oscillat or module (osc) 11.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 11.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 11.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 11.3.1 internal oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 11.3.1.1 internal oscillator trimming . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 11.3.1.2 internal to external clock switching . . . . . . . . . . . . . . . . . . . . . . 105 11.3.2 external oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 11.3.3 xtal oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 11.3.4 rc oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 11.4 oscillator module signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 11.4.1 crystal amplifier input pin (osc1) . . . . . . . . . . . . . . . . . . . . . . . . . 107 11.4.2 crystal amplifier output pin (osc 2/pta4/busclkx4). . . . . . . . . 108 11.4.3 oscillator enable signal (simoscen) . . . . . . . . . . . . . . . . . . . . . . 109 table of contents mc68hc908ql family data sheet motorola table of contents 11 11.4.4 xtal oscillator clock (xtalclk) . . . . . . . . . . . . . . . . . . . . . . . . . 109 11.4.5 rc oscillator clock (rcclk) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 11.4.6 internal oscillator clock (intclk) . . . . . . . . . . . . . . . . . . . . . . . . . 109 11.4.7 oscillator out 2 (busclkx4). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 11.4.8 oscillator out (busclkx2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 11.5 low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 11.5.1 wait mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 11.5.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 11.6 oscillator during break mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 11.7 config2 options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 11.8 input/output (i/o) registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 11.8.1 oscillator status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 11.8.2 oscillator trim register (osctrim) . . . . . . . . . . . . . . . . . . . . . . . 112 section 12. input/out put ports (ports) 12.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 12.2 port a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 12.2.1 port a data register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 12.2.2 data direction register a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 12.2.3 port a input pullup enable register . . . . . . . . . . . . . . . . . . . . . . . . 116 12.3 port b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 12.3.1 port b data register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 12.3.2 data direction register b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 12.3.3 port b input pullup enable register . . . . . . . . . . . . . . . . . . . . . . . . 119 section 13. system in tegration module (sim) 13.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 13.2 rst and irq pins initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 13.3 sim bus clock control and generation . . . . . . . . . . . . . . . . . . . . . . . . 121 13.3.1 bus timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 13.3.2 clock start-up from por . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 13.3.3 clocks in stop mode and wait mode . . . . . . . . . . . . . . . . . . . . . . . 124 13.4 reset and system initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 13.4.1 external pin reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 13.4.2 active resets from internal sources . . . . . . . . . . . . . . . . . . . . . . . 125 13.4.2.1 power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 13.4.2.2 computer operating properly (cop) reset . . . . . . . . . . . . . . . . 127 13.4.2.3 illegal opcode reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 13.4.2.4 illegal address reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 13.4.2.5 low-voltage inhibit (lvi) reset . . . . . . . . . . . . . . . . . . . . . . . . . 127 table of contents data sheet mc68hc908ql family 12 table of contents motorola 13.5 sim counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 13.5.1 sim counter during power-on reset . . . . . . . . . . . . . . . . . . . . . . 128 13.5.2 sim counter during stop mode recovery . . . . . . . . . . . . . . . . . . . 128 13.5.3 sim counter and reset states . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 13.6 exception control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 13.6.1 interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 13.6.1.1 hardware interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 13.6.1.2 swi instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 13.6.2 interrupt status registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 13.6.2.1 interrupt status register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 13.6.2.2 interrupt status register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 13.6.2.3 interrupt status register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 13.6.3 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 13.6.4 break interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 13.6.5 status flag protection in break mode . . . . . . . . . . . . . . . . . . . . . . 134 13.7 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 13.7.1 wait mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 13.7.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 13.8 sim registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 13.8.1 sim reset status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 13.8.2 break flag control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 13.8.3 break status register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 section 14. slave lin inte rface controller (slic) 14.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 14.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 14.3 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 14.3.1 power off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 14.3.2 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 14.3.3 slic disabled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 14.3.4 slic run . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 14.3.5 slic wait (core specific). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 14.3.6 wakeup from slic wait with cpu in wait . . . . . . . . . . . . . . . . . . 144 14.3.7 slic stop (core specific). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 14.3.8 normal and emulation mode operation (core specific). . . . . . . . . 145 14.3.9 special mode operation (core specific) . . . . . . . . . . . . . . . . . . . . 145 14.3.10 low-power options (core specific) . . . . . . . . . . . . . . . . . . . . . . . . 145 14.4 external signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 14.4.1 slctx ? slic transmit pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 14.4.2 slcrx ? slic receive pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 14.5 memory map/register definiti on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 14.6 slic registers and control bi ts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 14.6.1 slic control register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 14.6.2 slic control register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 table of contents mc68hc908ql family data sheet motorola table of contents 13 14.6.3 slic status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 14.6.4 slic prescaler register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 14.6.5 slic bit time registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 14.6.6 slic state vector register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 14.6.6.1 lin mode operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 14.6.6.2 byte transfer mode operation . . . . . . . . . . . . . . . . . . . . . . . . . . 155 14.6.7 slic data length code register . . . . . . . . . . . . . . . . . . . . . . . . . . 156 14.6.8 slic identifier and data registers . . . . . . . . . . . . . . . . . . . . . . . . . 158 14.7 initialization/application info rmation . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 14.7.1 lin message frame header . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 14.7.2 lin data field. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 14.7.3 lin checksum field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 14.7.4 slic module constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 14.8 slcsv interrupt handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 14.9 slic module initialization procedure . . . . . . . . . . . . . . . . . . . . . . . . . . 162 14.9.1 lin mode initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 14.9.2 byte transfer mode initialization . . . . . . . . . . . . . . . . . . . . . . . . . . 163 14.10 handling lin message headers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 14.10.1 lin message headers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 14.10.2 possible errors on message headers . . . . . . . . . . . . . . . . . . . . . . 167 14.11 handling command message frames . . . . . . . . . . . . . . . . . . . . . . . . . 167 14.11.1 standard command message frames. . . . . . . . . . . . . . . . . . . . . . 167 14.11.2 extended command message frames . . . . . . . . . . . . . . . . . . . . . 169 14.11.3 possible errors on command message da ta. . . . . . . . . . . . . . . . . 170 14.12 handling request lin message frames . . . . . . . . . . . . . . . . . . . . . . . 170 14.12.1 standard request message frames . . . . . . . . . . . . . . . . . . . . . . . 172 14.12.2 extended request message frames . . . . . . . . . . . . . . . . . . . . . . . 173 14.12.3 transmit abort . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 14.12.4 possible errors on request message da ta . . . . . . . . . . . . . . . . . . 174 14.13 handling imsg to minimize interrupts . . . . . . . . . . . . . . . . . . . . . . . . . 174 14.14 sleep and wakeup operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 14.15 polling operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 14.16 lin data integrity checking methods . . . . . . . . . . . . . . . . . . . . . . . . . . 175 14.17 high-speed lin operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 14.18 byte transfer mode operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 14.19 oscillator trimming with slic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 14.20 digital receive filter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 14.20.1 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 14.20.2 performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 table of contents data sheet mc68hc908ql family 14 table of contents motorola section 15. timer interface module (tim) 15.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 15.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 15.3 pin name conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 15.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 15.4.1 tim counter prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 15.4.2 input capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 15.4.3 output compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 15.4.3.1 unbuffered output compare. . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 15.4.3.2 buffered output compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 15.4.4 pulse width modulation (pwm) . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 15.4.4.1 unbuffered pwm signal generation. . . . . . . . . . . . . . . . . . . . . . 193 15.4.4.2 buffered pwm signal generation . . . . . . . . . . . . . . . . . . . . . . . . 194 15.4.4.3 pwm initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 15.5 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 15.6 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 15.7 tim during break interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 15.8 input/output signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 15.8.1 tim clock pin (pta2/tclk). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 15.8.2 tim channel i/o pins (pta0/tch0 and pta1/tch1) . . . . . . . . . . 196 15.9 input/output registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 15.9.1 tim status and control register . . . . . . . . . . . . . . . . . . . . . . . . . . 197 15.9.2 tim counter registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 15.9.3 tim counter modulo registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 15.9.4 tim channel status and control registers . . . . . . . . . . . . . . . . . . 200 15.9.5 tim channel registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 section 16. development support 16.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 16.2 break module (brk). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 16.2.1 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 16.2.1.1 flag protection during break interrupt s . . . . . . . . . . . . . . . . . . . 207 16.2.1.2 tim during break interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 16.2.1.3 cop during break interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 16.2.2 break module registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 16.2.2.1 break status and control register . . . . . . . . . . . . . . . . . . . . . . . 208 16.2.2.2 break address registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 16.2.2.3 break auxiliary register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 16.2.2.4 break status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 16.2.2.5 break flag control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 16.2.3 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 table of contents mc68hc908ql family data sheet motorola table of contents 15 16.3 monitor module (mon) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 16.3.1 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 16.3.1.1 normal monitor mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 16.3.1.2 forced monitor mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 16.3.1.3 monitor vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 16.3.1.4 data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 16.3.1.5 break signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 16.3.1.6 baud rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 16.3.1.7 commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 16.3.2 security. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 section 17. electri cal specifications 17.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 17.2 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 17.3 functional operating range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226 17.4 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226 17.5 5-v dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 17.6 control timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228 17.7 typical 5-v output drive characteristics . . . . . . . . . . . . . . . . . . . . . . . 229 17.8 5-v oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230 17.9 3.3-v dc electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . 231 17.10 typical 3.3-v output drive characteristics. . . . . . . . . . . . . . . . . . . . . . 232 17.11 3.3-v control timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233 17.12 3.3-v oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233 17.13 supply current characteristic s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234 17.14 analog-to-digital converter characteristics . . . . . . . . . . . . . . . . . . . . . 236 17.15 timer interface module characteristics . . . . . . . . . . . . . . . . . . . . . . . . 237 17.16 memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238 section 18. ordering information and mechanical specifications 18.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239 18.2 mc order numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239 18.3 16-pin plastic dual in-line package (case #648d) . . . . . . . . . . . . . . . 240 18.4 16-pin small outline integrated circuit package (case #751g) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240 18.5 16-pin thin shrink small outline package (case #948f) . . . . . . . . . . 241 table of contents data sheet mc68hc908ql family 16 table of contents motorola mc68hc908ql family data sheet motorola general description 17 data sheet ? mc68hc908ql4 family section 1. general description 1.1 introduction the mc68hc908ql4 is a member of t he low-cost, high-performance m68hc08 family of 8-bit microcontroller units (m cus). the m68hc08 family is a complex instruction set computer (cisc) with a von neumann architecture. all mcus in the family use the enhanced m68hc08 ce ntral processor unit (cpu08) and are available with a variety of modules, memory sizes and types , and package types. 0.4 1.2 features features include: high-performance m68hc08 cpu core fully upward-compatible objec t code with m68hc05 family 5-v and 3.3-v operating voltages (v dd ) 8-mhz internal bus operation at 5 v, 4-mhz at 3.3 v trimmable internal oscillator ? selectable 3.2 or 6.4 mhz internal bus operation ? 8-bit trim capability allows 0.4% accuracy (1) ? 25% untrimmed table 1-1. summary of device variations device memory size analog-to-digital converter pin count mc68hc908ql4 4096 bytes flash 6 ch, 10 bit 16 pins mc68hc908ql3 4096 bytes flash ? 16 pins mc68hc908ql2 2048 bytes flash 6 ch, 10 bit 16 pins 1. 5% guaranteed accuracy over entire temp erature and voltage rang e after trimming. lin communication easily maintained under all conditions using slic module. general description data sheet mc68hc908ql family 18 general description motorola slave lin interface controller (slic) module ? full lin messaging buffering of identifier and 8 data bytes ? automatic baud rate and lin message frame synchronization: no prior programming of bit rate required, 1?20 kbps lin bus speed operation all lin messages will be received (no message loss due to synchronization process) input clock tolerance as high as 50%, allowing internal oscillator to remain untrimmed incoming break symbols allowed to be 10 to 20 bit times without message loss supports automatic software trimming of internal oscillator using lin synchronization data ? automatic processing and verification of lin synch break and synch byte ? automatic checksum calculation and verification with error reporting ? maximum of 2 interrupts per lin message frame ? full lin error checking and reporting ? high-speed lin capability up to 83.33 kbps to 120.00 kbps ? configurable digital receive filter auto wakeup from stop capability in-system flash programming flash security (1) on-chip in-application programmable flash memory (with internal program/erase voltage generation) ? mc68hc908ql4, mc68hc908ql3 ? 4096 bytes ? mc68hc908ql2 ? 2048 bytes read-only memory (rom) ? mc68hc908ql4, mc68hc908ql3 ? 4096 bytes ? mc68hc908ql2 ? 2048 bytes 128 bytes of on-chip random-access memory (ram) 2-channel, 16-bit timer interface modul e (tim) with external clock source input 6-channel, 10-bit analog-to-digital converter (adc) on mc68hc908ql4 and mc68hc908ql2 13 bidirectional input/output (i/o) lines and one input only: ? six shared with keyboard interrupt function ? six shared with adc ? two shared with tim ? two shared with slc 1. no security feature is absolutely secure. howe ver, motorola?s strategy is to make reading or copying the flash difficult for unauthorized users. general description mcu block diagram mc68hc908ql family data sheet motorola general description 19 ? one shared with reset ? one input only shared with external interrupt (irq) ? high current sink/source capability ? selectable pullups on all ports, selectable on an individual bit basis ? three-state ability on all port pins 6-bit keyboard interrupt with wakeup feature (kbi) low-voltage inhibit (lvi) module features: ? software selectable trip point in config register system protection features: ? computer operating properly (cop) watchdog ? low-voltage detection with reset ? illegal opcode detection with reset ? illegal address detection with reset external asynchronous interrupt pin with internal pullup (irq ) shared with general-purpose input pin master asynchronous reset pin (rst ) shared with general-purpose input/output (i/o) pin power-on reset internal pullups on irq and rst to reduce external components memory mapped i/o registers power saving stop and wait modes available packages: ? 16-pin plastic dual in-line package (pdip) ? 16-pin small outline integrated circuit (soic) package ? 16-pin thin shrink small outline package (tssop) features of the cpu08 include the following: enhanced hc05 programming model extensive loop control functions 16 addressing modes (eight more than the hc05) 16-bit index register and stack pointer memory-to-memory data transfers fast 8 8 multiply instruction fast 16/8 divide instruction binary-coded decimal (bcd) instructions optimization for controller applications efficient c language support 1.3 mcu bl ock diagram figure 1-1 shows the structure of the mc68hc908ql4. general description data sheet mc68hc908ql family 20 general description motorola figure 1-1. block diagram rst , irq : pins have internal (about 30 k ? ) pull up pta0, pta1, pta3?pta5: high cu rrent sink and s ource capability pta0?pta5: pins have programm able keyboard interrupt and pull up adc pins only available on mc68hc908ql4 and mc68hc908ql2 pta0/ad0/kbi0 pta1/ad1/tch1/kbi1 pta2/irq /kbi2/tclk pta3/rst /kbi3 pta4/osc2/ad2/kbi4 pta5/osc1/ad3/kbi5 ptb0/tch0 ptb1 ptb2/ad4 ptb3/ad5 ptb4/slcrx ptb5/slctx ptb6 ptb7 power supply keyboard interrupt module clock generator (oscillator) system integration module single interrupt module break module power-on reset module 2-ch 16-bit timer module cop module monitor rom v dd v ss 128 bytes ram mc68hc908ql4 and mc68hc908ql3: 4096 bytes mc68hc908ql2: 2048 bytes user flash pta ddra ptb ddrb slave lin interface controller 6-channel 10-bit adc m68hc08 cpu general description pin functions mc68hc908ql family data sheet motorola general description 21 figure 1-2. mcu pin assignments 1.4 pin functions table 1-2 provides a description of the pin functions. 1 2 3 4 5 6 7 8 pta0/kbi0 ptb5/slctx ptb6 ptb2 v ss pta2/irq /kbi2/tclk pta1/tch1/kbi1 pta5/osc1/kbi5 16-pin assignment mc68hc908ql3 pdip/soic v dd ptb4/slcrx ptb3 ptb7 pta4/osc2/kbi4 pta3/rst /kbi3 ptb0/tch0 ptb1 1 2 3 4 5 6 7 16 15 14 13 12 11 10 8 ptb5/slctx ptb6 ptb2 pta2/irq /kbi2/tclk pta1/tch1/kbi1 16-pin assignment mc68hc908ql3 tssop ptb4/slcrx ptb3 ptb7 pta3/rst /kbi3 ptb0/tch0 ptb1 pta4/osc2/kbi4 pta5/osc1/kbi5 pta0/kbi0 v ss v dd 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 pta0/ad0/kbi0 ptb5/slctx ptb6 ptb2/ad4 v ss pta2/irq /kbi2/tclk pta1/ad1/tch1/kbi1 pta5/osc1/ad3/kbi5 16-pin assignment mc68hc908ql4 and mc68hc908ql2 pdip/soic v dd ptb4/slcrx ptb3/ad5 ptb7 pta4/osc2/ad2/kbi4 pta3/rst /kbi3 ptb0/tch0 ptb1 1 2 3 4 5 6 7 16 15 14 13 12 11 10 9 8 ptb5/slctx ptb6 ptb2/ad4 pta2/irq /kbi2/tclk pta1/ad1/tch1/kbi1 16-pin assignment mc68hc908ql4 and mc68hc908ql2 tssop ptb4/slcrx ptb3/ad5 ptb7 pta3/rst /kbi3 ptb0/tch0 ptb1 pta4/osc2/ad2/kbi4 pta5/osc1/ad3/kbi5 pta0/ad0/kbi0 v ss v dd 16 15 14 13 12 11 10 9 9 table 1-2. pin functions pin name description input/output v dd power supply power v ss power supply ground power pta0 pta0 ? general purpose i/o port input/output ad0 ? a/d channel 0 input input kbi0 ? keyboard interrupt input 0 input general description data sheet mc68hc908ql family 22 general description motorola pta1 pta1 ? general purpose i/o port input/output ad1 ? a/d channel 1 input input tch1 ? timer channel 1 i/o input/output kbi1? keyboard interrupt input 1 input pta2 pta2 ? general purpose input-only port input irq ? external interrupt with programmable pullup and schmitt trigger input input kbi2 ? keyboard interrupt input 2 input tclk ? external clock source input for the tim module input pta3 pta3 ? general purpose i/o port input/output rst ? reset input, active low with internal pullup and schmitt trigger input input kbi3 ? keyboard interrupt input 3 input pta4 pta4 ? general purpose i/o port input/output osc2 ? xtal oscillator output (xtal option only) rc or internal oscillator output (osc2en = 1 in ptapue register) output output ad2 ? a/d channel 2 input input kbi4 ? keyboard interrupt input 4 input pta5 pta5 ? general purpose i/o port input/output osc1 ? xtal, rc, or external oscillator input input ad3 ? a/d channel 3 input input kbi5 ? keyboard interrupt input 5 input ptb0 ptb0 ? general purpose i/o port input/output tch0 ? timer channel 0 i/o input/output ptb1 ptb1 ? general purpose i/o port input/output ptb2 ptb2 ? general purpose i/o port input/output ad4 ? a/d channel 4 input input ptb3 ptb3 ? general purpose i/o port input/output ad5 ? a/d channel 5 input input ptb4 ptb4 ? general purpose i/o port input/output slcrx ? slc receive input input ptb5 ptb5 ? general purpose i/o port input/output slctx ? slc transmit output output ptb6, ptb7 general-purpose i/o port input/output table 1-2. pin functions (continued) pin name description input/output general description pin function priority mc68hc908ql family data sheet motorola general description 23 1.5 pin function priority table 1-3 is meant to resolve the priority if multiple functions are enabled on a single pin. note: upon reset all pins come up as input ports regardless of the priority table. table 1-3. function priority in shared pins pin name highest-to-lowest priority sequence pta0 ad0 tch1 kbi0 pta0 pta1 ad1 kbi1 pta1 pta2 irq kbi2 tclk pta2 pta3 rst kbi3 pta3 pta4 osc2 ad2 kbi4 pta4 pta5 osc1 ad3 kbi5 pta5 ptb0 tch0 ptb0 ptb1 ptb1 ptb2 ad4 ptb2 ptb3 ad5 ptb3 ptb4 slcrx ptb4 ptb5 slctx ptb5 general description data sheet mc68hc908ql family 24 general description motorola mc68hc908ql family data sheet motorola memory 25 data sheet ? mc68hc908ql4 family section 2. memory 2.1 introduction the central processor unit (cpu08) can address 64 kbytes of memory space. the memory map, shown in figure 2-1 , includes: 4096 bytes of user flash for mc68hc908ql4 and mc68hc908ql3 2048 bytes of user flash for mc68hc908ql2 128 bytes of random access memory (ram) 48 bytes of user-defined vectors, located in flash 350 bytes of monitor read-only memory (rom) 674 bytes of flash program and eras e routines, located in auxiliary rom 2.2 unimplemented memory locations accessing a reserved location can have unpredictable effects on mcu operation. in figure 2-1 and in register figures in this document, unimplemented locations are shaded. 2.3 reserved memory locations accessing a reserved location can have unpredictable effects on mcu operation. in figure 2-1 and in register figures in this document, reserved locations are marked with the word reserved or with the letter r. memory data sheet mc68hc908ql family 26 memory motorola $0000 $0051 i/o registers 81 bytes $0052 $007f unimplemented 47 bytes $0080 $00ff ram 128 bytes $0100 $2b7d unimplemented 10,878 bytes unimplemented 10,878 bytes $0100 $2b7d $2b7e $2e1f auxiliary rom 674 bytes auxiliary rom 674 bytes $2b7e $2e1f $2e20 $edff unimplemented 49120 bytes unimplemented 51168 bytes $2e20 $f5ff $ee00 $fdff flash memory mc68hc908ql4 and mc68hc908ql3 4096 bytes flash memory 2048 bytes $f600 $fdff $fe00 $fe0f misc registers 16 bytes mc68hc908ql2 memory map $fe00 $fe0f unimplemented 16 bytes $fe10 $ff7d monitor rom 350 bytes $ff7e $ffbd unimplemented 64 bytes $ffbe $ffc1 misc registers 4 bytes $ffc2 $ffcf unimplemented 14 bytes $ffd0 $ffff user vectors 48 bytes figure 2-1. memory map memory input/output (i/o) section mc68hc908ql family data sheet motorola memory 27 2.4 input/output (i/o) section addresses $0000?$0051, shown in figure 2-2 , contain most of the control, status, and data registers. additional miscella neous registers have these addresses: $fe00 ? break status register, bsr $fe01 ? reset status register, srsr $fe02 ? break auxiliary register, brkar $fe03 ? break flag control register, bfcr $fe04 ? interrupt status register 1, int1 $fe05 ? interrupt status register 2, int2 $fe06 ? interrupt status register 3, int3 $fe07 ? reserved $fe08 ? flash control register, flcr $fe09 ? break address register high, brkh $fe0a ? break address register low, brkl $fe0b ? break status and control register, brkscr $fe0c ? lvi status register, lvisr $fe0d?$fe0f ? reserved $ffbe ? flash block protect register, flbpr $ffbf ? reserved $ffc0 ? internal osc trim value ? optional $ffc1 ? reserved $ffff ? cop control register, copctl memory data sheet mc68hc908ql family 28 memory motorola addr.register name bit 7654321bit 0 $0000 port a data register (pta) see page 114. read: 0 awul pta5 pta4 pta3 pta2 pta1 pta0 write: reset:u0uuuuuu $0001 port b data register (ptb) see page 117. read: ptb7 ptb6 ptb5 ptb4 ptb3 ptb2 ptb1 ptb0 write: reset: unaffected by reset $0002 unimplemented $0003 unimplemented $0004 data direction register a (ddra) see page 115. read: 0 0 ddra5 ddra4 ddra3 0 ddra1 ddra0 write: reset:00000000 $0005 data direction register b (ddrb) see page 117. read: ddrb7 ddrb6 ddrb5 ddrb4 ddrb3 ddrb2 ddrb1 ddrb0 write: reset:00000000 $0006 $000a unimplemented $000b port a input pullup enable register (ptapue) see page 116. read: osc2en 0 ptapue5 ptapue4 ptapue3 ptapue2 ptapue1 ptapue0 write: reset:00000000 $000c port b input pullup enable register (ptbpue) see page 119. read: ptbpue7 ptbpue6 ptbpue5 ptbpue4 ptbpue3 ptbpue2 ptbpue1 ptbpue0 write: reset:00000000 $000d $0019 unimplemented $001a keyboard status and control register (kbscr) see page 96. read:0000keyf0 imaskk modek write: ackk reset:00000000 $001b keyboard interrupt enable register (kbier) see page 97. read: 0 awuie kbie5 kbie4 kbie3 kbie2 kbie1 kbie0 write: reset:00000000 $001c unimplemented = unimplemented r = reserved u = unaffected figure 2-2. control, status, and data registers (sheet 1 of 7) memory input/output (i/o) section mc68hc908ql family data sheet motorola memory 29 $001d irq status and control register (intscr) see page 89. read:0000irqf0 imask mode write: ack reset:00000000 $001e configuration register 2 (config2) (1) see page 64. read: r r r oscopt1 oscopt0 irqpud irqen rsten write: reset:00000000 (2) 1. one-time writable register after each reset. 2. rsten reset to 0 by a power-on reset (por) only. $001f configuration register 1 (config1) (1) see page 64. read: coprs lvistop lvirstd lvipwrd lvi5or3 ssrec stop copd write: reset:00000 (2) 000 1. one-time writable register after each reset. 2. lvi5or3 reset to 0 by a power-on reset (por) only. $0020 tim status and control register (tsc) see page 197. read: tof toie tstop 00 ps2 ps1 ps0 write: 0 trst reset:00100000 $0021 tim counter register high (tcnth) see page 199. read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset:00000000 $0022 tim counter register low (tcntl) see page 199. read:bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 write: reset:00000000 $0023 tim counter modulo register high (tmodh) see page 199. read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset:11111111 $0024 tim counter modulo register low (tmodl) see page 199. read: bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 write: reset:11111111 $0025 tim channel 0 status and control register (tsc0) see page 200. read: ch0f ch0ie ms0b ms0a els0b els0a tov0 ch0max write: 0 reset:00000000 $0026 tim channel 0 register high (tch0h) see page 203. read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset: indeterminate after reset addr.register name bit 7654321bit 0 = unimplemented r = reserved u = unaffected figure 2-2. control, status, and data registers (sheet 2 of 7) memory data sheet mc68hc908ql family 30 memory motorola $0027 tim channel 0 register low (tch0l) see page 203. read: bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 write: reset: indeterminate after reset $0028 tim channel 1 status and control register (tsc1) see page 200. read: ch1f ch1ie 0 ms1a els1b els1a tov1 ch1max write: 0 reset:00000000 $0029 tim channel 1 register high (tch1h) see page 203. read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset: indeterminate after reset $002a tim channel 1 register low (tch1l) see page 203. read: bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 write: reset: indeterminate after reset $002b $0035 unimplemented $0036 oscillator status and control register (oscstat) see page 111. read: rrrrrbfsecgon ecgst write: reset:00000000 $0037 unimplemented $0038 oscillator trim register (osctrim) see page 112. read: trim7 trim6 trim5 trim4 trim3 trim2 trim1 trim0 write: reset:10000000 $0039 $003b unimplemented $003c adc status and control register (adscr) see page 52. read: coco aien adco adch4 adch3 adch2 adch1 adch0 write: reset:00011111 $003d adc data high register (adrh) see page 53. read:ad9ad8ad7ad6ad5ad4ad3ad2 write: reset: unaffected by reset $003e adc data low register (adrl) see page 53. read:ad1ad0000000 write: reset: unaffected by reset addr.register name bit 7654321bit 0 = unimplemented r = reserved u = unaffected figure 2-2. control, status, and data registers (sheet 3 of 7) memory input/output (i/o) section mc68hc908ql family data sheet motorola memory 31 $003f adc clock register (adclk) see page 55. read: adiv2 adiv1 adiv0 adiclk mode1 mode0 r 0 write: reset:00000100 $0040 slic control register 1 (slcc1) see page 147. read: 0 0 initreq 0 waketx txabrt imsg slcie write: reset:00100000 $0041 slic control register 2 (slcc2) see page 148. read:0000 slcwcm btm 0 slce write: reset:00000000 $0042 slic status register (slcs) see page 149. read:slcact0initack0000 slcf write: reset:00100000 $0043 slic prescale register (slcp) see page 150. read: rxfp1 rxfp0 000000 write: reset:10000000 $0044 slic bit time register high (slcbth) see page 152. read: 0 0 0 bt12 bt11 bt10 bt9 bt8 write: reset:00000000 $0045 slic bit time register low (slcbtl) see page 152. read: bt7 bt6 bt5 bt4 bt3 bt2 bt1 0 write: reset:00000000 $0046 slic state vector register (slcsv) see page 152. read: 0 0 i3 i2 i1 i0 0 0 write: reset:00000000 $0047 slic data length code register (slcdlc) see page 157. read: txgo chkmod dlc5 dlc4 dlc3 dlc2 dlc1 dlc0 write: reset:00000000 $0048 slic identifier register (slcid) see page 158. read: r7 r6 r5 r4 r3 r2 r1 r0 write: t7 t6 t5 t4 t3 t2 t1 t0 reset:00000000 $0049 slic data register 7 (slcd7) see page 159. read: r7 r6 r5 r4 r3 r2 r1 r0 write: t7 t6 t5 t4 t3 t2 t1 t0 reset:00000000 $004a slic data register 6 (slcd6) see page 159. read: r7 r6 r5 r4 r3 r2 r1 r0 write: t7 t6 t5 t4 t3 t2 t1 t0 reset:00000000 addr.register name bit 7654321bit 0 = unimplemented r = reserved u = unaffected figure 2-2. control, status, and data registers (sheet 4 of 7) memory data sheet mc68hc908ql family 32 memory motorola $004b slic data register 5 (slcd5) see page 159. read: r7 r6 r5 r4 r3 r2 r1 r0 write: t7 t6 t5 t4 t3 t2 t1 t0 reset:00000000 $004c slic data register 4 (slcd4) see page 159. read: r7 r6 r5 r4 r3 r2 r1 r0 write: t7 t6 t5 t4 t3 t2 t1 t0 reset:00000000 $004d slic data register 3 (slcd3) see page 159. read: r7 r6 r5 r4 r3 r2 r1 r0 write: t7 t6 t5 t4 t3 t2 t1 t0 reset:00000000 $004e slic data register 2 (slcd2) see page 159. read: r7 r6 r5 r4 r3 r2 r1 r0 write: t7 t6 t5 t4 t3 t2 t1 t0 reset:00000000 $004f slic data register 1 (slcd1) see page 160. read: r7 r6 r5 r4 r3 r2 r1 r0 write: t7 t6 t5 t4 t3 t2 t1 t0 reset:00000000 $0050 slic data register 0 (slcd0) see page 160. read: r7 r6 r5 r4 r3 r2 r1 r0 write: t7 t6 t5 t4 t3 t2 t1 t0 reset:00000000 $0051 $005f unimplemented $fe00 break status register (bsr) see page 210. read: rrrrrr sbsw r write: see note 1 reset: 0 1. writing a 0 clears sbsw. $fe01 sim reset status register (srsr) see page 137. read: por pin cop ilop ilad modrst lvi 0 write: por:10000000 $fe02 break auxiliary register (brkar) see page 209. read:0000000 bdcop write: reset:00000000 $fe03 break flag control register (bfcr) see page 210. read: bcferrrrrrr write: reset: 0 addr.register name bit 7654321bit 0 = unimplemented r = reserved u = unaffected figure 2-2. control, status, and data registers (sheet 5 of 7) memory input/output (i/o) section mc68hc908ql family data sheet motorola memory 33 $fe04 interrupt status register 1 (int1) see page 89. read: 0 if5 if4 if3 0 if1 0 0 write:rrrrrrrr reset:00000000 $fe05 interrupt status register 2 (int2) see page 89. read: if14 0 0 if11 if10 if9 0 0 write:rrrrrrrr reset:00000000 $fe06 interrupt status register 3 (int3) see page 89. read:0000000if15 write:rrrrrrrr reset:00000000 $fe07 reserved rrrrrrrr $fe08 flash control register (flcr) see page 37. read:0000 hven mass erase pgm write: reset:00000000 $fe09 break address high register (brkh) see page 209. read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset:00000000 $fe0a break address low register (brkl) see page 209. read: bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 write: reset:00000000 $fe0b break status and control register (brkscr) see page 208. read: brke brka 000000 write: reset:00000000 $fe0c lvi status register (lvisr) see page 101. read:lviout000000r write: reset:00000000 $fe0d $fe0f reserved for flash test rrrrrrrr $ffb0 $ffbd unimplemented $ffbe flash block protect register (flbpr) see page 43. read: bpr7 bpr6 bpr5 bpr4 bpr3 bpr2 bpr1 0 write: reset:00000000 addr.register name bit 7654321bit 0 = unimplemented r = reserved u = unaffected figure 2-2. control, status, and data registers (sheet 6 of 7) memory data sheet mc68hc908ql family 34 memory motorola $ffbf unimplemented $ffc0 internal oscillator trim value (optional) read: trim7 trim6 trim5 trim4 trim3 trim2 trim1 trim0 write: reset:10000000 $ffc1 reserved rrrrrrrr $ffc2 $ffcf unimplemented $ffff cop control register (copctl) see page 69. read: low byte of reset vector write: writing clears cop counter (any value) reset: unaffected by reset addr.register name bit 7654321bit 0 = unimplemented r = reserved u = unaffected figure 2-2. control, status, and data registers (sheet 7 of 7) memory input/output (i/o) section mc68hc908ql family data sheet motorola memory 35 . table 2-1. vector addresses vector priority ve ctor address vector lowest highest if15 $ffde adc conversion complete vector (high) $ffdf adc conversion complete vector (low) if14 $ffe0 keyboard vector (high) $ffe1 keyboard vector (low) if13 if10 ? not used if9 $ffea slic vector (high) $ffeb slic vector (low) if8 if6 ? not used if5 $fff2 tim overflow vector (high) $fff3 tim overflow vector (low) if4 $fff4 tim channel 1 vector (high) $fff5 tim channel 1 vector (low) if3 $fff6 tim channel 0 vector (high) $fff7 tim channel 0 vector (low) if2 ? not used if1 $fffa irq vector (high) $fffb irq vector (low) ? $fffc swi vector (high) $fffd swi vector (low) ? $fffe reset vector (high) $ffff reset vector (low) memory data sheet mc68hc908ql family 36 memory motorola 2.5 random-access memory (ram) addresses $0080?$00ff are ram locations. the location of the stack ram is programmable. the 16-bit stack pointer al lows the stack to be anywhere in the 64-kbyte memory space. note: for correct operation, the stack pointer must point only to ram locations. before processing an interrupt, the central pr ocessor unit (cpu) uses five bytes of the stack to save the contents of the cpu registers. note: for m6805, m146805, and m68hc05 compatibility, the h register is not stacked. during a subroutine call, the cpu uses two bytes of the stack to store the return address. the stack pointer decrements during pushes and increments during pulls. note: be careful when using nested subroutines . the cpu may overwrite data in the ram during a subroutine or during the interrupt stacking operation. 2.6 flash memory (flash) the flash memory consists of an array of 4096 or 2048 bytes with an additional 48 bytes for user vectors. the minimum size of flash memory that can be erased is 64 bytes; and the maximum size of flash memory that can be programmed in a program cycle is 32 bytes (a row). prog ram and erase operations are facilitated through control bits in the flash control register (flcr). details for these operations appear later in this section. the address ranges for the user memory and vectors are: $ee00 ? $fdff; user memory, 4096 bytes: mc68hc908ql4 and mc68hc908ql3 $f600 ? $fdff; user memory, 2048 bytes: mc68hc908ql2 $ffd0 ? $ffff; user interrupt vectors, 48 bytes. note: an erased bit reads as 1 and a programmed bit reads as 0. a security feature prevents viewing of the flash contents. (1) 1. no security feature is absolutely secure. howe ver, motorola?s strategy is to make reading or copying the flash difficult for unauthorized users. memory flash memory (flash) mc68hc908ql family data sheet motorola memory 37 2.6.1 flash control register the flash control register (flcr) controls flash program and erase operations. hven ? high voltage enable bit this read/write bit enables high voltage from the charge pump to the memory for either program or erase operation. it can only be set if either pgm =1 or erase =1 and the proper sequence for program or erase is followed. 1 = high voltage enabled to array and charge pump on 0 = high voltage disabled to array and charge pump off mass ? mass erase control bit this read/write bit configures the memory for mass erase operation. 1 = mass erase operation selected 0 = mass erase operation unselected erase ? erase control bit this read/write bit configures the memory for erase operation. erase is interlocked with the pgm bit such that both bits cannot be equal to 1 or set to 1 at the same time. 1 = erase operation selected 0 = erase operation unselected pgm ? program control bit this read/write bit configures the memory for program operation. pgm is interlocked with the erase bit such that both bits cannot be equal to 1 or set to 1 at the same time. 1 = program operation selected 0 = program operation unselected address: $fe08 bit 7654321bit 0 read:0000 hven mass erase pgm write: reset:00000000 figure 2-3. flash control register (flcr) memory data sheet mc68hc908ql family 38 memory motorola 2.6.2 flash page erase operation use the following procedure to erase a page of flash memory. a page consists of 64 consecutive bytes starting from addresses $xx00, $xx40, $xx80, or $xxc0. the 48-byte user interrupt vectors area also forms a page. any flash memory page can be erased alone. 1. set the erase bit and clear the mass bit in the flash control register. 2. read the flash block protect register. 3. write any data to any flash location within the address range of the block to be erased. 4. wait for a time, t nvs (minimum 10 s). 5. set the hven bit. 6. wait for a time, t erase (minimum 1 ms or 4 ms). 7. clear the erase bit. 8. wait for a time, t nvh (minimum 5 s). 9. clear the hven bit. 10. after time, t rcv (typical 1 s), the memory can be accessed in read mode again. note: programming and erasing of flash locati ons cannot be performed by code being executed from the flash memory. while these operations must be performed in the order as shown, but other unrelated operations may occur between the steps. caution: a page erase of the vector page will erase the internal oscillator trim value at $ffc0. in applications that require more than 1000 program/erase cycles, use the 4 ms page erase specification to get improved long-term reliability. any application can use this 4 ms page erase specification. however, in applications where a flash location will be erased and reprogrammed less than 1000 times, and speed is important, use the 1 ms page erase specif ication to get a shorter cycle time. memory flash memory (flash) mc68hc908ql family data sheet motorola memory 39 2.6.3 flash mass erase operation use the following procedure to erase the entire flash memory to read as 1: 1. set both the erase bit and the mass bit in the flash control register. 2. read from the flash block protect register. 3. write any data to any flash address (1) within the flash memory address range. 4. wait for a time, t nvs (minimum 10 s). 5. set the hven bit. 6. wait for a time, t erase (minimum 4 ms). 7. clear the erase and mass bits. note: mass erase is disabled whene ver any block is protected (flbpr does not equal $ff). 8. wait for a time, t nvh (minimum 100 s). 9. clear the hven bit. 10. after time, t rcv (typical 1 s), the memory can be accessed in read mode again. note: programming and erasing of flash locati ons cannot be performed by code being executed from the flash memory. while these operations must be performed in the order as shown, but other unrelated operations may occur between the steps. caution: a mass erase will erase the intern al oscillator trim value at $ffc0. 1. when in monitor mode, with security sequence failed (see 16.3.2 security ), write to the flash block protect register instead of any flash address. memory data sheet mc68hc908ql family 40 memory motorola 2.6.4 flash program operation programming of the flash memory is done on a row basis. a row consists of 32 consecutive bytes starting from addresses $xx00, $xx20, $xx40, $xx60, $xx80, $xxa0, $xxc0, or $xxe0. use the followi ng step-by-step procedure to program a row of flash memory figure 2-4 shows a flowchart of the programming algorithm. note: only bytes which are currently $ff may be programmed. 1. set the pgm bit. this configures the memory for program operation and enables the latching of address and data for programming. 2. read from the flash block protect register. 3. write any data to any flash location within the address range desired. 4. wait for a time, t nvs (minimum 10 s). 5. set the hven bit. 6. wait for a time, t pgs (minimum 5 s). 7. write data to the flash address being programmed (1) . 8. wait for time, t prog (minimum 30 s). 9. repeat step 7 and 8 until all desired bytes within the row are programmed. 10. clear the pgm bit (1) . 11. wait for time, t nvh (minimum 5 s). 12. clear the hven bit. 13. after time, t rcv (typical 1 s), the memory can be accessed in read mode again. note: the cop register at location $ffff sh ould not be written between steps 5?12, when the hven bit is set. since this regi ster is located at a valid flash address, unpredictable behavior may occur if this location is written while hven is set. this program sequence is repeated throughout the memory until all data is programmed. note: programming and erasing of flash locati ons cannot be performed by code being executed from the flash memory. while these operations must be performed in the order shown, other unrelated operations may occur between the steps. do not exceed t prog maximum, see 17.16 memory characteristics . 1. the time between each flash address change, or the time between the last flash address programmed to clearing pgm bit, must not exceed the maximum programming time, t prog maximum. memory flash memory (flash) mc68hc908ql family data sheet motorola memory 41 2.6.5 flash protection due to the ability of the on-board charge pump to erase and program the flash memory in the target application, provisi on is made to protect blocks of memory from unintentional erase or program operations due to system malfunction. this protection is done by use of a flash blo ck protect register (flbpr). the flbpr determines the range of the flash memory which is to be protected. the range of the protected area starts from a lo cation defined by flbpr and ends to the bottom of the flash memory ($ffff). when the memory is protected, the hven bit cannot be set in either erase or program operations. note: in performing a program or erase operation, the flash block protect register must be read after setting the pgm or erase bit and before asserting the hven bit. when the flbpr is programmed with all 0s, the entire memory is protected from being programmed and erased. when all the bits are erased (all 1s), the entire memory is accessible for program and erase. when bits within the flbpr are programmed, they lock a block of memory. the address ranges are shown in 2.6.6 flash block protect register . once the flbpr is programmed with a value other than $ff, any erase or program of the flbpr or the protected block of flash memory is prohibited. mass erase is disabled whenever any block is protec ted (flbpr does not equal $ff). the flbpr itself can be erased or program med only with an external voltage, v tst , present on the irq pin. this voltage also allows entry from reset into the monitor mode. memory data sheet mc68hc908ql family 42 memory motorola figure 2-4. flash programming flowchart set hven bit write any data to any flash address within the row address range desired wait for a time, t nvs set pgm bit wait for a time, t pgs write data to the flash address to be programmed wait for a time, t prog clear pgm bit wait for a time, t nvh clear hven bit wait for a time, t rcv completed programming this row? y n end of programming the time between each flash address change (step 7to step 7), must not exceed the maximum programming time, t prog max. or the time between the last flash address programmed to clearing pgm bit (step 6 to step 10) notes: 1 3 4 5 6 7 8 10 11 12 13 algorithm for programming a row (32 bytes) of flash memory this row program algorithm assumes the row/s to be programmed are initially erased. 9 read the flash block protect register 2 memory flash memory (flash) mc68hc908ql family data sheet motorola memory 43 2.6.6 flash block protect register the flash block protect register is implemented as a byte within the flash memory, and therefore can only be written during a programming sequence of the flash memory. the value in this register determines the starting address of the protected range within the flash memory. bpr[7:0] ? flash protection register bits [7:0] these eight bits in flbpr represent bits [13:6] of a 16-bit memory address. bits [15:14] are 1s and bits [5:0] are 0s. the resultant 16-bit address is used for specifying the start address of the flash memory for block protection. the flash is protected from this start address to the end of flash memory, at $ffff. with this mechanism, the protect start address can be xx00, xx40, xx80, or xxc0 within the flash memory. see figure 2-6 and table 2-2 . figure 2-6. flash block protect start address address: $ffbe bit 7654321bit 0 read: bpr7 bpr6 bpr5 bpr4 bpr3 bpr2 bpr1 bpr0 write: reset:uuuuuuuu u = unaffected by reset. initial value from factory is 1. write to this register is by a programming sequence to the flash memory. figure 2-5. flash block protect register (flbpr) table 2-2. examples of protect start address bpr[7:0] start of address of protect range $00?$b8 the entire flash memory is protected. $b9 ( 1011 1001 ) $ee40 (11 10 1110 01 00 0000) $ba ( 1011 1010 ) $ee80 (11 10 1110 10 00 0000) $bb ( 1011 1011 ) $eec0 (11 10 1110 11 00 0000) $bc ( 1011 1100 ) $ef00 (11 10 1111 00 00 0000) and so on... $de ( 1101 1110 ) $f780 (11 11 0111 10 00 0000) $df ( 1101 1111 )$f7c0 (11 11 0111 11 00 0000) $fe ( 1111 1110 ) $ff80 (11 11 1111 10 00 0000) flbpr, osctrim, and vectors are protected $ff the entire flash memory is not protected. 0 0 0 0 0 1 1 flbpr value start address of 16-bit memory address flash block protect 0 memory data sheet mc68hc908ql family 44 memory motorola 2.6.7 wait mode putting the mcu into wait mode while the flash is in read mode does not affect the operation of the flash memory directly, but there will not be any memory activity since the cpu is inactive. the wait instruction should not be execut ed while performing a program or erase operation on the flash, or the operation will discontinue and the flash will be on standby mode. 2.6.8 stop mode putting the mcu into stop mode while the flash is in read mode does not affect the operation of the flash memory directly, but there will not be any memory activity since the cpu is inactive. the stop instruction should not be executed while performing a program or erase operation on the flash, or the operation will discontinue and the flash will be on standby mode note: standby mode is the power-saving mode of the flash module in which all internal control signals to the flash are inacti ve and the current consumption of the flash is at a minimum. mc68hc908ql family data sheet motorola analog-to-digital converter (adc) 45 data sheet ? mc68hc908ql4 family section 3. analog-to-digital converter (adc) 3.1 introduction this section describes the 10-bit analog-to-digital converter (adc). 3.2 features features of the adc module include: six channels with multiplexed input linear successive approximation with monotonicity 10-bit resolution single or continuous conversion conversion complete flag or conversion complete interrupt selectable adc clock left or right justified result left justified sign data mode 3.3 functional description the adc provides six pins for sampling external sources. an analog multiplexer allows the single adc converter to se lect one of the adc channels as adc voltage in (v adin ). v adin is converted by the successive approximation register-based analog-to-digital converter. when the conversion is completed, adc places the result in the adc data register and sets a flag or generates an interrupt. see figure 3-2 . 3.3.1 adc port i/o pins pta0, pta1, pta4, pta5, ptb2, and ptb3 are general-purpose i/o (input/output) pins that share with t he adc channels. the channel select bits define which adc channel/port pin will be used as the input signal. the adc overrides the port i/o logic by forcing that pin as input to the adc. the remaining adc channels/port pins are controlled by the port i/o logic and can be used as general-purpose i/o. writes to the port regi ster or data direction register (ddr) will not have any affect on the port pin that is selected by the adc. read of a port pin in use by the adc will return a logic 0. analog-to-digital converter (adc) data sheet mc68hc908ql family 46 analog-to-digital converter (adc) motorola figure 3-1. block diagram highlighting adc block and pins rst , irq : pins have internal (about 30 k ? ) pull up pta0, pta1, pta3?pta5: high current sink and source capability pta0?pta5: pins have programmable keyboard interrupt and pull up adc pins only available on mc68hc908ql4 and mc68hc908ql2 pta0/ad0/kbi0 pta1/ad1/tch1/kbi1 pta2/irq /kbi2/tclk pta3/rst /kbi3 pta4/osc2/ad2/kbi4 pta5/osc1/ad3/kbi5 ptb0/tch0 ptb1 ptb2/ad4 ptb3/ad5 ptb4/slcrx ptb5/slctx ptb6 ptb7 power supply keyboard interrupt module clock generator (oscillator) system integration module single interrupt module break module power-on reset module 2-ch 16-bit timer module cop module monitor rom v dd v ss 128 bytes ram mc68hc908ql4 and mc68hc908ql3: 4096 bytes mc68hc908ql2: 2048 bytes user flash pta ddra ptb ddrb slave lin interface controller 6-channel 10-bit adc m68hc08 cpu analog-to-digital converter (adc) functional description mc68hc908ql family data sheet motorola analog-to-digital converter (adc) 47 figure 3-2. adc block diagram 3.3.2 voltage conversion when the input voltage to the adc equals v refh , the adc converts the signal to $3ff (full scale). if the input voltage equals v refl , the adc converts it to $000. input voltages between v refh and v refl are a straight-line linear conversion. note: the adc input voltage must always be greater than v ssa and less than v dda . v refh must always be greater than or equal to v refl . connect the v dda pin to the same voltage potential as the v dd pin, and connect the v ssa pin to the same voltage potential as the v ss pin. the v dda pin should be routed carefully for maximum noise immunity. internal data bus read ddrx write ddrx reset write ptx read ptx ptx ddrx ptx interrupt logic channel select adc clock generator conversion complete adc (v adin ) adc clock cgmxclk bus clock adch4?adch0 adc data register aien coco disable disable adc channel x adiv2?adiv0 adiclk voltage in analog-to-digital converter (adc) data sheet mc68hc908ql family 48 analog-to-digital converter (adc) motorola 3.3.3 conversion time conversion starts after a write to the adc status and control register (adscr). one conversion will take between 16 and 17 adc clock cycles. the adivx and adiclk bits should be set to provide a 1-mhz adc clock frequency. 3.3.4 conversion in continuous conversion mode, the adc data register will be filled with new data after each conversion. data from the pr evious conversion will be overwritten whether that data has been read or not. conv ersions will continue until the adco bit is cleared. the coco bit is set after each conversion and will stay set until the next write of the adc status and control register or the next read of the adc data register. in single conversion mode, conversion begins with a write to the adscr. only one conversion occurs between writes to the adscr. 3.3.5 accuracy and precision the conversion process is monotonic and has no missing codes. 3.3.6 result justification the conversion result may be formatted in four different ways: 1. left justified 2. right justified 3. left justified sign data mode 4. 8-bit truncation mode all four of these modes are controlled using mode0 and mode1 bits located in the adc clock register (adclk). left justification will place the eight most significant bits (msb) in the corresponding adc data register high, adrh. this may be useful if the result is to be treated as an 8-bit result where the two least significant bits (lsb), located in the adc data register low, adrl, can be ignored. however, adrl must be read after adrh or else the interlocking will prevent a ll new conversions from being stored. right justification will place only the two msbs in the corresponding adc data register high, adrh, and the eight lsbs in adc data register low, adrl. this mode of operation typically is used when a 10-bit unsigned result is desired. 16 to 17 adc cycles adc frequency conversion time = number of bus cycles = conversion time bus frequency analog-to-digital converter (adc) functional description mc68hc908ql family data sheet motorola analog-to-digital converter (adc) 49 left justified sign data mode is similar to le ft justified mode with one exception. the msb of the 10-bit result, ad9 located in adrh, is complemented. this mode of operation is useful when a result, represented as a signed magnitude from mid-scale, is needed. finally, 8-bit truncati on mode will place the eight msbs in the adc data register low, adrl. the two lsbs are dropped. this mode of operation is used when compatibility wi th 8-bit adc designs are required. no interlocking between adrh and adrl is present. note: quantization error is affected when only the most significant eight bits are used as a result. see figure 3-3 . figure 3-3. bit truncation mode error ideal 10-bit characteristic with quantization = 1/2 ideal 8-bit characteristic with quantization = 1/2 10-bit truncated to 8-bit result when truncation is used, error from ideal 8-bit = 3/8 lsb due to non-ideal quantization. 000 001 002 003 004 005 006 007 008 009 00a 00b 000 001 002 003 8-bit result 10-bit result input voltage represented as 10-bit input voltage represented as 8-bit 1/2 2 1/2 4 1/2 6 1/2 8 1/2 1 1/2 3 1/2 5 1/2 7 1/2 9 1/2 1/2 2 1/2 1 1/2 analog-to-digital converter (adc) data sheet mc68hc908ql family 50 analog-to-digital converter (adc) motorola 3.4 monotonicity the conversion process is monotonic and has no missing codes. 3.5 interrupts when the aien bit is set, the adc module is capable of generating cpu interrupts after each adc conversion. a cpu interrupt is generated if the coco bit is at 0. the coco bit is not used as a conversion complete flag when interrupts are enabled. 3.6 low-power modes the wait and stop instruction can put the mcu in low power-consumption standby modes. 3.6.1 wait mode the adc continues normal operation during wait mode. any enabled cpu interrupt request from the adc can bring the mcu out of wait mode. if the adc is not required to bring the mcu out of wait mode, power down the adc by setting adch4?adch0 bits in the adc status and control register before executing the wait instruction. 3.6.2 stop mode the adc module is inactive after the execution of a stop instruction. any pending conversion is aborted. adc conversions resume when the mcu exits stop mode after an external interrupt. allow one conversion cycle to stabilize the analog circuitry. 3.7 i/o signals the adc module has six pi ns shared with i/o pins on port a and port b. 3.7.1 adc analog power pin (v ddad ) the adc analog portion uses v ddad as its power pin and is internally connected to the v dd pad. external filtering may be necessary to ensure clean v dd for good results. note: for maximum noise immunity, route v dd carefully and place bypass capacitors as close as possible to the package. v dd and v dda use the same pad on the mc68hc908ql4. analog-to-digital converter (adc) i/o registers mc68hc908ql family data sheet motorola analog-to-digital converter (adc) 51 3.7.2 adc analog ground pin (v ssad ) the adc analog portion uses v ssad as its ground pin and is internally connected to the v ssad pad. note: route v ss cleanly to avoid any offset errors. v dd and v dda use the same pad on the mc68hc908ql4. 3.7.3 adc voltage reference high pin (v refh ) the adc analog portion uses v refh as its upper voltage reference pin. by default, connect the v refh pin to the same voltage potential as v dd . external filtering is often necessary to ensure a clean v refh for good results. any noise present on this pin will be reflected and possibl y magnified in a/d conversion values. note: for maximum noise immunity, route v refh carefully and place bypass capacitors as close as possible to the package. routing v refh close and parallel to v refl may improve common mode noise rejection. v dd and v refh are connected on the mc68hc908ql4. 3.7.4 adc voltage reference low pin (v refl ) the adc analog portion uses v refl as its lower voltage reference pin. by default, connect the v refl pin to the same voltage potential as v ss . external filtering is often necessary to ensure a clean v refl for good results. any noise present on this pin will be reflected an d possibly magnified in a/d conversion values. note: for maximum noise immunity, route v refl carefully and, if not connected to v ss , place bypass capacitors as close as possible to the package. routing v refh close and parallel to v refl may improve common mode noise rejection. v ss and v refl are connected on the mc68hc908ql4. 3.7.5 adc voltage in (v adin ) v adin is the input voltage signal from one of the adc channels to the adc module. 3.8 i/o registers these i/o registers control and monitor adc operation: adc status and control register (adscr) adc data register (adrh and adrl) adc clock register (adclk) analog-to-digital converter (adc) data sheet mc68hc908ql family 52 analog-to-digital converter (adc) motorola 3.8.1 adc status and control register function of the adc status and contro l register (adscr) is described here. coco ? conversions complete bit when the aien bit is 0, the coco is a read-only bit which is set each time a conversion is completed except in the continuous conversion mode where it is set after the first conversion. this bit is cleared whenever the adscr is written or whenever the adr is read. if the aien bit is 1, the coco becomes a read/write bit, which should be cleared to 0 for cpu to service the adc interrupt request. reset clears this bit. 1 = conversion completed (aien = 0) 0 = conversion not completed (aien = 0)/cpu interrupt (aien = 1) aien ? adc interrupt enable bit when this bit is set, an interrupt is generated at the end of an adc conversion. the interrupt signal is cleared when the data register is read or the status/control register is written. reset clears the aien bit. 1 = adc interrupt enabled 0 = adc interrupt disabled adco ? adc continuous conversion bit when set, the adc will convert samples continuously and update the adr register at the end of each conversion. only one conversion is completed between writes to the adscr when this bit is cleared. reset clears the adco bit. 1 = continuous adc conversion 0 = one adc conversion adch4?adch0 ? adc channel select bits adch4?adch0 form a 5-bit field which is used to select one of 16 adc channels. only eight channels, ad7?ad0, are available on this mcu. the channels are detailed in table 3-1 . care should be taken when using a port pin as both an analog and digital input simultaneously to prevent switching noise from corrupting the analog signal. the adc subsystem is turned off when the channel select bits are all set to 1. this feature allows for reduced power consumption for the mcu when the adc is not being used. note: recovery from the disabled state requires one conversion cycle to stabilize. address: $003c bit 7654321bit 0 read: coco aien adco adch4 adch3 adch2 adch1 adch0 write: reset:00011111 figure 3-4. adc status and control register (adscr) analog-to-digital converter (adc) i/o registers mc68hc908ql family data sheet motorola analog-to-digital converter (adc) 53 the voltage levels supplied from internal reference nodes, as specified in table 3-1 , are used to verify the operation of the adc converter both in production test and for user applications. 3.8.2 adc data register high and data register low 3.8.2.1 left justified mode in left justified mode, the adrh register ho lds the eight msbs of the 10-bit result. the only difference from left justified mode is that the ad9 is complemented. the adrl register holds the two lsbs of the 10-bit result. all other bits read as 0. adrh and adrl are updated each ti me an adc single channel conversion completes. reading adrh latches the contents of adrl until adrl is read. all subsequent results will be lost until the adrh and adrl reads are completed. table 3-1. mux channel select (1) 1. if any unused channels are selected, the resulting adc conversion will be unknown or reserved. adch4 adch3 adch2 adch1 adch0 input select 0 0 0 0 0 pta0/ad0/kbi0 0 0 0 0 1 pta1/ad1/kbi1 0 0 0 1 0 pta4/osc2/ad2/kbi2 0 0 0 1 1 pta5/osc1/ad3/kbi5 00100 ptb2/ad4 00101 ptb3/ad5 0 1 0 1 1 1 1 0 0 0 unused 11101 v dda 11110 v ssa 11111 adc power off address: $003d adrh bit 7654321bit 0 read: ad9 ad8 ad7 ad6 ad5 ad4 ad3 ad2 write: reset: unaffected by reset address: $003e adrl read:ad1ad0000000 write: reset: unaffected by reset = unimplemented figure 3-5. adc data register high (adrh) and low (adrl) analog-to-digital converter (adc) data sheet mc68hc908ql family 54 analog-to-digital converter (adc) motorola 3.8.2.2 right justified mode in right justified mode, the adrh register holds the two msbs of the 10-bit result. all other bits read as 0. the adrl register holds the eight lsbs of the 10-bit result. adrh and adrl are updated each ti me an adc single channel conversion completes. reading adrh latches the contents of adrl until adrl is read. all subsequent results will be lost until the adrh and adrl reads are completed. 3.8.2.3 left justified signed data mode in left justified signed data mode, the adrh register holds the eight msbs of the 10-bit result. the only difference from left justified mode is that the ad9 is complemented. the adrl register holds the two lsbs of the 10-bit result. all other bits read as 0. adrh and adrl are updated each time an adc single channel conversion completes. reading adrh latches the contents of adrl until adrl is read. all subsequent results will be lost until the adrh and adrl reads are completed. address: $003d adrh bit 7654321bit 0 read:000000ad9ad8 write: reset: unaffected by reset address: $003e adrl read: ad7 ad6 ad5 ad4 ad3 ad2 ad1 ad0 write: reset: unaffected by reset = unimplemented figure 3-6. adc data register high (adrh) and low (adrl) address: $003d adrh bit 7654321bit 0 read: ad9 ad8 ad7 ad6 ad5 ad4 ad3 ad2 write: reset: unaffected by reset address: $003e adrl read:ad1ad0000000 write: reset: unaffected by reset = unimplemented figure 3-7. adc data register high (adrh) and low (adrl) analog-to-digital converter (adc) i/o registers mc68hc908ql family data sheet motorola analog-to-digital converter (adc) 55 3.8.2.4 eight bit truncation mode in 8-bit truncation mode, the adrl register holds the eight msbs of the 10-bit result. the adrh register is unused and reads as 0. the adrl register is updated each time an adc single channel conversion completes. in 8-bit mode, the adrl register contains no interlocking with adrh. 3.8.3 adc clock register the adc clock register (adclk) selects the clock frequency for the adc. adiv2?adiv0 ? adc clock prescaler bits adiv2?adiv0 form a 3-bit field which selects the divide ratio used by the adc to generate the internal adc clock. table 3-2 shows the available clock configurations. the adc clock shou ld be set to approximately 1 mhz. address: $003d adrh bit 7654321bit 0 read:00000000 write: reset: unaffected by reset address: $003e adrl read: ad9 ad8 ad7 ad6 ad5 ad4 ad3 ad2 write: reset: unaffected by reset = unimplemented figure 3-8. adc data register high (adrh) and low (adrl) address: $003f bit 7654321bit 0 read: adiv2 adiv1 adiv0 adiclk mode1 mode0 r 0 write: reset:00000100 = unimplemented r = reserved figure 3-9. adc clock register (adclk) table 3-2. adc clock divide ratio adiv2 adiv1 adiv0 adc clock rate 0 0 0 adc input clock 1 0 0 1 adc input clock 2 0 1 0 adc input clock 4 0 1 1 adc input clock 8 1 x (1) 1. x = don?t care x (1) adc input clock 16 analog-to-digital converter (adc) data sheet mc68hc908ql family 56 analog-to-digital converter (adc) motorola adiclk ? adc input clock select bit adiclk selects either the bus clock or the oscillator output clock (cgmxclk) as the input clock source to generate the internal adc clock. reset selects cgmxclk as the adc clock source. 1 = internal bus clock 0 = oscillator output clock (cgmxclk) the adc requires a clock rate of approximately 1 mhz for correct operation. if the selected clock source is not fast enough, the adc will generate incorrect conversions. see 17.14 analog-to-digital converter characteristics . mode1 and mode0 ? modes of result justification bits mode1 and mode0 select among four modes of operation. the manner in which the adc conversion results will be placed in the adc data registers is controlled by these modes of operati on. reset returns right-justified mode. 00 = 8-bit truncation mode 01 = right justified mode 10 = left justified mode 11 = left justified signed data mode f adic = f cgmxclk or bus frequency adiv[2:0] ? 1 mhz mc68hc908ql family data sheet motorola auto wakeup module (awu) 57 data sheet ? mc68hc908ql4 family section 4. auto wakeup module (awu) 4.1 introduction this section describes the auto wak eup module (awu). the awu generates a periodic interrupt during stop mode to wake the part up without requiring an external signal. figure 4-2 is a block diagram of the awu. 4.2 features features of the auto wakeup module include: one internal interrupt with separate interrupt enable bit, sharing the same keyboard interrupt vector and keyboard interrupt mask bit. exit from low-power stop mode without external signals. selectable timeout periods of 16 milliseconds or 512 milliseconds. dedicated low power internal oscillator separate from the main system clock sources. figure 4-1 provides a summary of the input/output (i/o) registers used in conjuction with the awu. addr.register name bit 7654321bit 0 $0000 port a data register (pta) see page 60. read: 0 awul pta5 pta4 pta3 pta2 pta1 pta0 write: reset: unaffected by reset $001a keyboard status and control register (kbscr) see page 60. read:0000keyf0 imaskk modek write: ackk reset:00000000 $001b keyboard interrupt enable register (kbier) see page 61. read: 0 awuie kbie5 kbie4 kbie3 kbie2 kbie1 kbie0 write: reset:00000000 = unimplemented figure 4-1. awu register summary auto wakeup module (awu) data sheet mc68hc908ql family 58 auto wakeup module (awu) motorola 4.3 functional description the function of the auto wakeup logic is to generate periodic wakeup requests to bring the microcontroller unit (mcu) ou t of stop mode. the wakeup requests are treated as regular keyboard interrupt requests, with the difference that instead of a pin, the interrupt signal is generated by an internal logic. writing the awuie bit in the keyboard interrupt enable register enables or disables the auto wakeup interrupt input (see figure 4-2 ). a logic 1 applied to the awuireq input with auto wakeup interrupt request enabled, latches an auto wakeup interrupt request. auto wakeup latch, awul, can be read directly from the bit 6 position of port a data register (pta). this is a read-only bit wh ich is occupying an empty bit position on pta. no pta associated registers, such as pta6 data direction or pta6 pullup exist for this bit. entering stop mode will enable the auto wak eup generation logic. an internal rc oscillator (exclusive for the auto wake up feature) drives the wakeup request generator. once the overflow count is reached in the generator counter, a wakeup request, awuireq, is latched and sent to the kbi logic. see figure 4-1 . figure 4-2. auto wakeup interrupt request generation logic d r v dd int rc osc en 32 khz clk rst overflow autowugen short coprs (from config1) 1 = div 2 9 0 = div 2 14 e reset ackk clear rst reset clk (cgmxclk) busclkx4 istop awuireq clrlogic reset awul to pta read, bit 6 q awuie to kbi interrupt logic (see figure 4-2 ) auto wakeup module (awu) wait mode mc68hc908ql family data sheet motorola auto wakeup module (awu) 59 entering stop mode will enable the auto wak eup generation logic. an internal rc oscillator (exclusive for the auto wake up feature) drives the wakeup request generator. once the overflow count is reached in the generator counter, a wakeup request, awuireq, is latched and sent to the kbi logic. see figure 4-1 . wakeup interrupt requests will only be serviced if the associated interrupt enable bit, awuie, in kbier is set. the awu shares the keyboard interrupt vector. the overflow count can be selected from two options defined by the coprs bit in config1. this bit was ?borrowed? from the computer operating properly (cop) using the fact that the cop feature is idle (no mcu clock available) in stop mode. the typical values of the periodic wakeup request are (at room temperature): coprs = 0: 650 ms @ 5 v, 950 ms @ 3 v coprs = 1: 16 ms @ 5 v, 23 ms @ 3 v the auto wakeup rc oscillator is hi ghly dependent on operating voltage and temperature. this feature is not recommended for use as a time-keeping function. the wakeup request is latched to allow the interrupt source identification. the latched value, awul, can be read directly from the bit 6 position of pta data register. this is a read-only bit which is occupying an empty bit position on pta. no pta associated registers, such as pta6 data, pta6 direction, and pta6 pullup exist for this bit. the latch can be cleared by writing to the ackk bit in the kbscr register. reset also clears the latch. awuie bit in kbi interrupt enable register (see figure 4-2 ) has no effect on awul reading. the awu oscillator and counters are i nactive in normal operating mode and become active only upon entering stop mode. 4.4 wait mode the awu module remains inactive in wait mode. 4.5 stop mode when the awu module is enabled (awuie = 1 in the keyboard interrupt enable register) it is activated automatically upon entering stop mode. clearing the imaskk bit in the keyboard status and control register enables keyboard interrupt requests to bring the mcu out of stop mode. the awu counters start from ?0? each time stop mode is entered. 4.6 input/output registers the awu shares registers with the keyboard interrupt (kbi) module and the port a i/o module. the following i/o registers control and monitor operation of the awu: port a data register (pta) keyboard interrupt status and control register (kbscr) keyboard interrupt enable register (kbier) auto wakeup module (awu) data sheet mc68hc908ql family 60 auto wakeup module (awu) motorola 4.6.1 port a i/o register the port a data register (pta) contains a data latch for the state of the awu interrupt request, in addition to the data latches for port a. awul ? auto wakeup latch this is a read-only bit which has the value of the auto wakeup interrupt request latch. the wakeup request signal is generated internally. there is no pta6 port or any of the associated bits such as pta6 data direction or pullup bits. 1 = auto wakeup interrupt request is pending 0 = auto wakeup interrupt request is not pending note: pta5?pta0 bits are not used in conjucti on with the auto wakeup feature. to see a description of these bits, see 12.2.1 port a data register . 4.6.2 keyboard status and control register the keyboard status and control register (kbscr): flags keyboard/auto wakeup interrupt requests acknowledges keyboard/auto wakeup interrupt requests masks keyboard/auto wakeup interrupt requests bits 7?4 ? not used these read-only bits always read as 0s. keyf ? keyboard flag bit this read-only bit is set when a keyboard interrupt is pending on port a or auto wakeup. reset clears the keyf bit. 1 = keyboard/auto wakeup interrupt pending 0 = no keyboard/auto wakeup interrupt pending address: $0000 bit 7654321bit 0 read: 0 awul pta5 pta4 pta3 pta2 pta1 pta0 write: reset: 0 0 unaffected by reset = unimplemented figure 4-3. port a data register (pta) address: $001a bit 7654321bit 0 read:0000keyf0 imaskk modek write: ackk reset:00000000 = unimplemented figure 4-4. keyboard status and control register (kbscr) auto wakeup module (awu) input/output registers mc68hc908ql family data sheet motorola auto wakeup module (awu) 61 ackk ? keyboard acknowledge bit writing a 1 to this write-only bit clears the keyboard/auto wakeup interrupt request on port a and auto wakeup logic. ackk always reads as 0. reset clears ackk. imaskk? keyboard interrupt mask bit writing a 1 to this read/write bit prevents the output of the keyboard interrupt mask from generating interrupt requests on port a or auto wakeup. reset clears the imaskk bit. 1 = keyboard/auto wakeup interrupt requests masked 0 = keyboard/auto wakeup interrupt requests not masked note: modek is not used in conjuction with the auto wakeup feature. to see a description of this bit, see 9.7.1 keyboard status and control register . 4.6.3 keyboard interrupt enable register the keyboard interrupt enable register (kbier) enables or disables the auto wakeup to operate as a keyboard/auto wakeup interrupt input. awuie ? auto wakeup interrupt enable bit this read/write bit enables the auto wakeup interrupt input to latch interrupt requests. reset clears awuie. 1 = auto wakeup enabled as interrupt input 0 = auto wakeup not enabled as interrupt input note: kbie5?kbie0 bits are not used in conjucti on with the auto wakeup feature. to see a description of these bits, see 9.7.2 keyboard interrupt enable register . address: $001b bit 7654321bit 0 read: 0 awuie kbie5 kbie4 kbie3 kbie2 kbie1 kbie0 write: reset:00000000 = unimplemented figure 4-5. keyboard interrupt enable register (kbier) auto wakeup module (awu) data sheet mc68hc908ql family 62 auto wakeup module (awu) motorola mc68hc908ql family data sheet motorola configuration register (config) 63 data sheet ? mc68hc908ql4 family section 5. configurat ion register (config) 5.1 introduction this section describes the configurati on registers (config1 and config2). the configuration registers enable or disable the following options: stop mode recovery time (32 busclkx4 cycles or 4096 busclkx4 cycles) stop instruction computer operating properly module (cop) cop reset period (coprs): (2 13 ?2 4 ) busclkx4 or (2 18 ?2 4 ) busclkx4 low-voltage inhibit (lvi) enable and trip voltage selection osc option selection irq pin rst pin auto wakeup timeout period 5.2 functional description the configuration registers are used in the initialization of various options. the configuration registers can be written once after each reset. most of the configuration register bits are cleared duri ng reset. since the various options affect the operation of the microcontroller unit (mcu) it is recommended that this register be written immediately after reset. the c onfiguration register is located at $001e and $001f, and may be read at anytime. note: the config registers are one-time writable by the user after each reset. upon a reset, the config registers default to predetermined settings as shown in figure 5-1 and figure 5-2 . configuration register (config) data sheet mc68hc908ql family 64 configuration register (config) motorola oscopt1 and oscopt0 ? selection bits for oscillator option (0, 0) internal oscillator (0, 1) external oscillator (1, 0) external rc oscillator (1, 1) external xtal oscillator irqpud ? irq pin pullup control bit 1 = internal pullup is disconnected 0 = internal pullup is connected between irq pin and v dd irqen ? irq pin function selection bit 1 = interrupt request function active in pin 0 = interrupt request function inactive in pin rsten ? rst pin function selection 1 = reset function active in pin 0 = reset function inactive in pin note: the rsten bit is cleared by a power-on re set (por) only. other resets will leave this bit unaffected. coprs (out of stop mode) ? cop reset period selection bit 1 = cop reset short cycle = (2 13 ? 2 4 ) address: $001e bit 76 54 321bit 0 read: r r r oscopt1 oscopt0 irqpud irqen rsten write: reset: por: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u 0 r = reserved u = unaffected figure 5-1 configuration register 2 (config2) address: $001f bit 7 6 5 4 3 2 1 bit 0 read: coprs lvistop lvirstd lvipwrd lvi5or3 ssrec stop copd write: reset: por: 0 0 0 0 0 0 0 0 u 0 0 0 0 0 0 0 u = unaffected figure 5-2 configuration register 1 (config1) configuration register (config) functional description mc68hc908ql family data sheet motorola configuration register (config) 65 lvistop ? lvi enable in stop mode bit when the lvipwrd bit is clear, setting the lvistop bit enables the lvi to operate during stop mode. reset clears lvistop. 1 = lvi enabled during stop mode 0 = lvi disabled during stop mode lvirstd ? lvi reset disable bit lvirstd disables the reset signal from the lvi module. 1 = lvi module resets disabled 0 = lvi module resets enabled lvipwrd ? lvi power disable bit lvipwrd disables the lvi module. 1 = lvi module power disabled 0 = lvi module power enabled lvi5or3 ? lvi 5-v or 3.3-v operating mode bit lvi5or3 selects the voltage operating mode of the lvi module. the voltage mode selected for the lvi should match the operating v dd for the lvi?s voltage trip points for each of the modes. 1 = lvi operates in 5-v mode 0 = lvi operates in 3.3-v mode note: the lvi5or3 bit is cleared by a power-on re set (por) only. other resets will leave this bit unaffected. ssrec ? short stop recovery bit ssrec enables the cpu to exit stop mode with a delay of 32 busclkx4 cycles instead of a 4096 busclkx4 cycle delay. 1 = stop mode recovery after 32 busclkx4 cycles 0 = stop mode recovery after 4096 busclkx4 cycles note: exiting stop mode by an lvi reset will result in the long stop recovery. when using the lvi during normal operati on but disabling during stop mode, the lvi will have an enable time of t en . the system stabilization time for power-on reset and long stop recovery (both 4096 busclkx4 cycles) gives a delay longer than the lvi enable time for these startup scenarios. there is no period where the mcu is not protected from a low-power condition. however, when using the short stop recovery configur ation option, the 32 busclkx4 delay must be greater than the lvi?s turn on time to avoid a period in startup where the lvi is not protecting the mcu. stop ? stop instruction enable bit stop enables the stop instruction. 1 = stop instruction enabled 0 = stop instruction treated as illegal opcode copd ? cop disable bit copd disables the cop module. 1 = cop module disabled 0 = cop module enabled configuration register (config) data sheet mc68hc908ql family 66 configuration register (config) motorola mc68hc908ql family data sheet motorola computer operating properly (cop) 67 data sheet ? mc68hc908ql4 family section 6. computer op erating properly (cop) 6.1 introduction the computer operating properly (cop) m odule contains a free-running counter that generates a reset if allowed to overflow. the cop module helps software recover from runaway code. prevent a cop reset by clearing the cop counter periodically. the cop module can be dis abled through the copd bit in the configuration 1 (config1) register. 6.2 functional description figure 6-1. cop block diagram 1. see section 13. system integration module (sim) for more details. copctl write busclkx4 reset vector fetch sim reset circuit reset status register internal reset sources (1) sim module clear stages 5?12 12-bit sim counter clear all stages copd (from config1) reset copctl write clear cop module copen (from sim) cop clock cop timeout cop rate select (coprs from config1) 6-bit cop counter cop counter computer operating properly (cop) data sheet mc68hc908ql family 68 computer operating properly (cop) motorola the cop counter is a free-running 6-bit counter preceded by the 12-bit system integration module (sim) counter. if no t cleared by software, the cop counter overflows and generates an asynchronous reset after 2 18 ?2 4 or 2 13 ?2 4 busclkx4 cycles; depending on the state of the cop rate select bit, coprs, in configuration register 1. with a 2 18 ?2 4 busclkx4 cycle overflow option, a 8-mhz crystal gives a cop timeout period of 32.766 ms. writing any value to location $ffff before an overflow occurs prevents a cop reset by clearing the cop counter and stages 12?5 of the sim counter. note: service the cop immediately after reset and before entering or after exiting stop mode to guarantee the maximum time before the first cop counter overflow. a cop reset pulls the rst pin low (if the rsten bit is set in the config1 register) for 32 busclkx4 cycles and sets the cop bit in the reset status register (rsr). see 13.8.1 sim reset status register . note: place cop clearing instructions in the main program and not in an interrupt subroutine. such an interrupt subrouti ne could keep the cop from generating a reset even while the main program is not working properly. 6.3 i/o signals the following paragraphs describe the signals shown in figure 6-1 . 6.3.1 busclkx4 busclkx4 is the oscillator output signal . busclkx4 frequency is equal to the crystal frequency or the rc-oscillator frequency. 6.3.2 copctl write writing any value to the cop control register (copctl) (see 6.4 cop control register ) clears the cop counter and clears bits 12?5 of the sim counter. reading the cop control register returns the low byte of the reset vector. 6.3.3 power-on reset the power-on reset (por) circuit in the sim clears the sim counter 4096 busclkx4 cycles after power up. 6.3.4 internal reset an internal reset clears the sim counter and the cop counter. 6.3.5 reset vector fetch a reset vector fetch occurs when the vector address appears on the data bus. a reset vector fetch clears the sim counter. computer operating properly (cop) cop control register mc68hc908ql family data sheet motorola computer operating properly (cop) 69 6.3.6 copd (cop disable) the copd signal reflects the state of the cop disable bit (copd) in the configuration register (config). see section 5. configuration register (config) . 6.3.7 coprs (cop rate select) the coprs signal reflects the state of the cop rate select bit (coprs) in the configuration register 1 (config1). see section 5. configuration register (config) . 6.4 cop cont rol register the cop control register (copctl) is lo cated at address $ffff and overlaps the reset vector. writing any value to $ffff clears the cop counter and starts a new timeout period. reading location $ffff returns the low byte of the reset vector. 6.5 interrupts the cop does not generate cpu interrupt requests. 6.6 monitor mode the cop is disabled in monitor mode when v tst is present on the irq pin. 6.7 low-power modes the wait and stop instructions put the mcu in low power-consumption standby modes. 6.7.1 wait mode the cop remains active during wait mode. if cop is enabled, a reset will occur at cop timeout. address: $ffff bit 7654321bit 0 read: low byte of reset vector write: clear cop counter reset: unaffected by reset figure 6-2. cop control register (copctl) computer operating properly (cop) data sheet mc68hc908ql family 70 computer operating properly (cop) motorola 6.7.2 stop mode stop mode turns off the busclkx4 input to the cop and clears the sim counter. service the cop immediately before entering or after exiting stop mode to ensure a full cop timeout period after entering or exiting stop mode. 6.8 cop module during break mode the cop is disabled during a break inte rrupt with monitor mode when bdcop bit is set in break auxiliary register (brkar). mc68hc908ql family data sheet motorola central processor unit (cpu) 71 data sheet ? mc68hc908ql4 family section 7. central processor unit (cpu) 7.1 introduction the m68hc08 cpu (central processo r unit) is an enhanced and fully object-code-compatible version of the m68hc05 cpu. the cpu08 reference manual (motorola document order number cpu08rm/ad) contains a description of the cpu instruction set, addressing modes, and architecture. 7.2 features features of the cpu include: object code fully upward-compatible with m68hc05 family 16-bit stack pointer with stack manipulation instructions 16-bit index register with x-register manipulation instructions 8-mhz cpu internal bus frequency 64-kbyte program/data memory space 16 addressing modes memory-to-memory data moves without using accumulator fast 8-bit by 8-bit multiply and 16-bit by 8-bit divide instructions enhanced binary-coded decimal (bcd) data handling modular architecture with expandable inte rnal bus definition for extension of addressing range beyond 64 kbytes low-power stop and wait modes central processor unit (cpu) data sheet mc68hc908ql family 72 central processor unit (cpu) motorola 7.3 cpu registers figure 7-1 shows the five cpu registers. cpu registers are not part of the memory map. figure 7-1. cpu registers 7.3.1 accumulator the accumulator is a general-purpose 8-bit register. the cpu uses the accumulator to hold operands and the re sults of arithmetic/logic operations. accumulator (a) index register (h:x) stack pointer (sp) program counter (pc) condition code register (ccr) carry/borrow flag zero flag negative flag interrupt mask half-carry flag two?s complement overflow flag v11hinzc h x 0 0 0 0 7 15 15 15 70 bit 7654321bit 0 read: write: reset: unaffected by reset figure 7-2. accumulator (a) central processor unit (cpu) cpu registers mc68hc908ql family data sheet motorola central processor unit (cpu) 73 7.3.2 index register the 16-bit index register allows indexed addressing of a 64-kbyte memory space. h is the upper byte of the index regist er, and x is the lower byte. h:x is the concatenated 16-bit index register. in the indexed addressing modes , the cpu uses the contents of the index register to determine the conditional address of the operand. the index register can serve also as a temporary data storage location. 7.3.3 stack pointer the stack pointer is a 16-bit register that contains the address of the next location on the stack. during a reset, the stack pointer is preset to $00ff. the reset stack pointer (rsp) instruction sets the least significant byte to $ff and does not affect the most significant byte. the stack point er decrements as data is pushed onto the stack and increments as data is pulled from the stack. in the stack pointer 8-bit offset and 16-bit offset addressing modes, the stack pointer can function as an i ndex register to access data on the stack. the cpu uses the contents of the stack pointer to determine the conditional address of the operand. note: the location of the stack is arbitrary and may be relocated anywhere in random-access memory (ram). moving the sp out of page 0 ($0000 to $00ff) frees direct address (page 0) space. for correct operation, the stack pointer must point only to ram locations. bit 151413121110987654321 bit 0 read: write: reset:00000000 xxxxxxxx x = indeterminate figure 7-3. index register (h:x) bit 151413121110987654321 bit 0 read: write: reset:0000000011111111 figure 7-4. stack pointer (sp) central processor unit (cpu) data sheet mc68hc908ql family 74 central processor unit (cpu) motorola 7.3.4 program counter the program counter is a 16-bit register that contains the address of the next instruction or operand to be fetched. normally, the program counter automati cally increments to the next sequential memory location every time an instruction or operand is fetched. jump, branch, and interrupt operations load the program counter with an address other than that of the next sequential location. during reset, the program counter is loaded with the reset vector address located at $fffe and $ffff. the vector address is the address of the first instruction to be executed after exiting the reset state. 7.3.5 condition code register the 8-bit condition code register contains the interrupt mask and five flags that indicate the results of the instruction just executed. bits 6 and 5 are set permanently to 1. the following paragraphs describe the functions of the condition code register. v ? overflow flag the cpu sets the overflow flag when a two's complement overflow occurs. the signed branch instructions bgt, bge, ble, and blt use the overflow flag. 1 = overflow 0 = no overflow bit 151413121110987654321 bit 0 read: write: reset: loaded with vector from $fffe and $ffff figure 7-5. program counter (pc) bit 7654321bit 0 read: v11hinzc write: reset:x11x1xxx x = indeterminate figure 7-6. condition code register (ccr) central processor unit (cpu) cpu registers mc68hc908ql family data sheet motorola central processor unit (cpu) 75 h ? half-carry flag the cpu sets the half-carry flag when a carry occurs between accumulator bits 3 and 4 during an add-without-carry (add) or add-with-carry (adc) operation. the half-carry flag is required for binary-coded decimal (bcd) arithmetic operations. the daa instruction uses the states of the h and c flags to determine the appropriate correction factor. 1 = carry between bits 3 and 4 0 = no carry between bits 3 and 4 i ? interrupt mask when the interrupt mask is set, all maskable cpu interrupts are disabled. cpu interrupts are enabled when the interrupt mask is cleared. when a cpu interrupt occurs, the interrupt mask is set automatically after the cpu registers are saved on the stack, but before the interrupt vector is fetched. 1 = interrupts disabled 0 = interrupts enabled note: to maintain m6805 family compatibility, the upper byte of the index register (h) is not stacked automatically. if the interrupt service routine modifies h, then the user must stack and unstack h using the pshh and pulh instructions. after the i bit is cleared, t he highest-priority interrupt request is serviced first. a return-from-interrupt (rti) instruction pulls the cpu registers from the stack and restores the interrupt mask from the stack. after any reset, the interrupt mask is set and can be cleared only by the clear interrupt mask software instruction (cli). n ? negative flag the cpu sets the negative flag when an arithmetic operation, logic operation, or data manipulation produces a negative result, setting bit 7 of the result. 1 = negative result 0 = non-negative result z ? zero flag the cpu sets the zero flag when an arithmetic operation, logic operation, or data manipulation produces a result of $00. 1 = zero result 0 = non-zero result c ? carry/borrow flag the cpu sets the carry/borrow flag when an addition operation produces a carry out of bit 7 of the accumulator or when a subtraction operation requires a borrow. some instructions ? such as bit test and branch, shift, and rotate ? also clear or set the carry/borrow flag. 1 = carry out of bit 7 0 = no carry out of bit 7 central processor unit (cpu) data sheet mc68hc908ql family 76 central processor unit (cpu) motorola 7.4 arithmetic/ logic unit (alu) the alu performs the arithmetic and logic operations defined by the instruction set. refer to the cpu08 reference manual (motorola document order number cpu08rm/ad) for a description of the instructions and addressing modes and more detail about the architecture of the cpu. 7.5 low-power modes the wait and stop instructions put the mcu in low power-consumption standby modes. 7.5.1 wait mode the wait instruction: clears the interrupt mask (i bit) in the condition code register, enabling interrupts. after exit from wait mode by interrupt, the i bit remains clear. after exit by reset, the i bit is set. disables the cpu clock 7.5.2 stop mode the stop instruction: clears the interrupt mask (i bit) in the condition code register, enabling external interrupts. after exit from st op mode by external interrupt, the i bit remains clear. after exit by reset, the i bit is set. disables the cpu clock after exiting stop mode, the cpu clock begins running after the oscillator stabilization delay. 7.6 cpu during break interrupts if a break module is present on the mcu, the cpu starts a break interrupt by: loading the instruction register with the swi instruction loading the program counter with $fffc:$fffd or with $fefc:$fefd in monitor mode the break interrupt begins after completion of the cpu instruction in progress. if the break address register match occurs on the last cycle of a cpu instruction, the break interrupt begins immediately. a return-from-interrupt instruction (rti) in the break routine ends the break interrupt and returns the mcu to normal operation if the break interrupt has been deasserted. central processor unit (cpu) instruction set summary mc68hc908ql family data sheet motorola central processor unit (cpu) 77 7.7 instruction set summary table 7-1 provides a summary of the m68hc08 instruction set. table 7-1. instruction set summary (sheet 1 of 7) source form operation description effect on ccr address mode opcode operand cycles vh i nzc adc # opr adc opr adc opr adc opr ,x adc opr ,x adc ,x adc opr ,sp adc opr ,sp add with carry a (a) + (m) + (c) ? imm dir ext ix2 ix1 ix sp1 sp2 a9 b9 c9 d9 e9 f9 9ee9 9ed9 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 add # opr add opr add opr add opr ,x add opr ,x add ,x add opr ,sp add opr ,sp add without carry a (a) + (m) ? imm dir ext ix2 ix1 ix sp1 sp2 ab bb cb db eb fb 9eeb 9edb ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 ais # opr add immediate value (signed) to sp sp (sp) + (16 ? m) ??????imm a7 ii 2 aix # opr add immediate value (signed) to h:x h:x (h:x) + (16 ? m) ??????imm af ii 2 and # opr and opr and opr and opr ,x and opr ,x and ,x and opr ,sp and opr ,sp logical and a (a) & (m) 0 ? ? ? imm dir ext ix2 ix1 ix sp1 sp2 a4 b4 c4 d4 e4 f4 9ee4 9ed4 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 asl opr asla aslx asl opr ,x asl ,x asl opr ,sp arithmetic shift left (same as lsl) ?? dir inh inh ix1 ix sp1 38 48 58 68 78 9e68 dd ff ff 4 1 1 4 3 5 asr opr asra asrx asr opr ,x asr opr ,x asr opr ,sp arithmetic shift right ?? dir inh inh ix1 ix sp1 37 47 57 67 77 9e67 dd ff ff 4 1 1 4 3 5 bcc rel branch if carry bit clear pc (pc) + 2 + rel ? (c) = 0 ??????rel 24 rr 3 bclr n , opr clear bit n in m mn 0 ?????? dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 11 13 15 17 19 1b 1d 1f dd dd dd dd dd dd dd dd 4 4 4 4 4 4 4 4 bcs rel branch if carry bit set (same as blo) pc (pc) + 2 + rel ? (c) = 1 ??????rel 25 rr 3 beq rel branch if equal pc (pc) + 2 + rel ? (z) = 1 ??????rel 27 rr 3 c b0 b7 0 b0 b7 c central processor unit (cpu) data sheet mc68hc908ql family 78 central processor unit (cpu) motorola bge opr branch if greater than or equal to (signed operands) pc (pc) + 2 + rel ? (n v ) = 0 ??????rel 90 rr 3 bgt opr branch if greater than (signed operands) pc (pc) + 2 + rel ? (z) | (n v ) = 0 ??????rel 92 rr 3 bhcc rel branch if half carry bit clear pc (pc) + 2 + rel ? (h) = 0 ??????rel 28 rr 3 bhcs rel branch if half carry bit set pc (pc) + 2 + rel ? (h) = 1 ??????rel 29 rr 3 bhi rel branch if higher pc (pc) + 2 + rel ? (c) | (z) = 0 ??????rel 22 rr 3 bhs rel branch if higher or same (same as bcc) pc (pc) + 2 + rel ? (c) = 0 ??????rel 24 rr 3 bih rel branch if irq pin high pc (pc) + 2 + rel ? irq = 1 ??????rel 2f rr 3 bil rel branch if irq pin low pc (pc) + 2 + rel ? irq = 0 ??????rel 2e rr 3 bit # opr bit opr bit opr bit opr ,x bit opr ,x bit ,x bit opr ,sp bit opr ,sp bit test (a) & (m) 0 ? ? ? imm dir ext ix2 ix1 ix sp1 sp2 a5 b5 c5 d5 e5 f5 9ee5 9ed5 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 ble opr branch if less than or equal to (signed operands) pc (pc) + 2 + rel ? (z) | (n v ) = 1 ??????rel 93 rr 3 blo rel branch if lower (same as bcs) pc (pc) + 2 + rel ? (c) = 1 ??????rel 25 rr 3 bls rel branch if lower or same pc (pc) + 2 + rel ? (c) | (z) = 1 ??????rel 23 rr 3 blt opr branch if less than (signed operands) pc (pc) + 2 + rel ? (n v ) = 1 ??????rel 91 rr 3 bmc rel branch if interrupt mask clear pc (pc) + 2 + rel ? (i) = 0 ??????rel 2c rr 3 bmi rel branch if minus pc (pc) + 2 + rel ? (n) = 1 ??????rel 2b rr 3 bms rel branch if interrupt mask set pc (pc) + 2 + rel ? (i) = 1 ??????rel 2d rr 3 bne rel branch if not equal pc (pc) + 2 + rel ? (z) = 0 ??????rel 26 rr 3 bpl rel branch if plus pc (pc) + 2 + rel ? (n) = 0 ??????rel 2a rr 3 bra rel branch always pc (pc) + 2 + rel ??????rel 20 rr 3 brclr n , opr , rel branch if bit n in m clear pc (pc) + 3 + rel ? (mn) = 0 ????? dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 01 03 05 07 09 0b 0d 0f dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr 5 5 5 5 5 5 5 5 brn rel branch never pc (pc) + 2 ??????rel 21 rr 3 table 7-1. instruction set summary (sheet 2 of 7) source form operation description effect on ccr address mode opcode operand cycles vh i nzc central processor unit (cpu) instruction set summary mc68hc908ql family data sheet motorola central processor unit (cpu) 79 brset n , opr , rel branch if bit n in m set pc (pc) + 3 + rel ? (mn) = 1 ????? dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 00 02 04 06 08 0a 0c 0e dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr 5 5 5 5 5 5 5 5 bset n , opr set bit n in m mn 1 ?????? dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 10 12 14 16 18 1a 1c 1e dd dd dd dd dd dd dd dd 4 4 4 4 4 4 4 4 bsr rel branch to subroutine pc (pc) + 2; push (pcl) sp (sp) ? 1; push (pch) sp (sp) ? 1 pc (pc) + rel ??????rel ad rr 4 cbeq opr,rel cbeqa # opr,rel cbeqx # opr,rel cbeq opr, x+ ,rel cbeq x+ ,rel cbeq opr, sp ,rel compare and branch if equal pc (pc) + 3 + rel ? (a) ? (m) = $00 pc (pc) + 3 + rel ? (a) ? (m) = $00 pc (pc) + 3 + rel ? (x) ? (m) = $00 pc (pc) + 3 + rel ? (a) ? (m) = $00 pc (pc) + 2 + rel ? (a) ? (m) = $00 pc (pc) + 4 + rel ? (a) ? (m) = $00 ?????? dir imm imm ix1+ ix+ sp1 31 41 51 61 71 9e61 dd rr ii rr ii rr ff rr rr ff rr 5 4 4 5 4 6 clc clear carry bit c 0 ?????0inh 98 1 cli clear interrupt mask i 0 ??0???inh 9a 2 clr opr clra clrx clrh clr opr ,x clr ,x clr opr ,sp clear m $00 a $00 x $00 h $00 m $00 m $00 m $00 0??01? dir inh inh inh ix1 ix sp1 3f 4f 5f 8c 6f 7f 9e6f dd ff ff 3 1 1 1 3 2 4 cmp # opr cmp opr cmp opr cmp opr ,x cmp opr ,x cmp ,x cmp opr ,sp cmp opr ,sp compare a with m (a) ? (m) ?? imm dir ext ix2 ix1 ix sp1 sp2 a1 b1 c1 d1 e1 f1 9ee1 9ed1 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 com opr coma comx com opr ,x com ,x com opr ,sp complement (one?s complement) m (m ) = $ff ? (m) a (a ) = $ff ? (m) x (x ) = $ff ? (m) m (m ) = $ff ? (m) m (m ) = $ff ? (m) m (m ) = $ff ? (m) 0?? 1 dir inh inh ix1 ix sp1 33 43 53 63 73 9e63 dd ff ff 4 1 1 4 3 5 cphx # opr cphx opr compare h:x with m (h:x) ? (m:m + 1) ?? imm dir 65 75 ii ii+1 dd 3 4 table 7-1. instruction set summary (sheet 3 of 7) source form operation description effect on ccr address mode opcode operand cycles vh i nzc central processor unit (cpu) data sheet mc68hc908ql family 80 central processor unit (cpu) motorola cpx # opr cpx opr cpx opr cpx ,x cpx opr ,x cpx opr ,x cpx opr ,sp cpx opr ,sp compare x with m (x) ? (m) ?? imm dir ext ix2 ix1 ix sp1 sp2 a3 b3 c3 d3 e3 f3 9ee3 9ed3 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 daa decimal adjust a (a) 10 u?? inh 72 2 dbnz opr,rel dbnza rel dbnzx rel dbnz opr, x ,rel dbnz x ,rel dbnz opr, sp ,rel decrement and branch if not zero a (a) ? 1 or m (m) ? 1 or x (x) ? 1 pc (pc) + 3 + rel ? (result) 0 pc (pc) + 2 + rel ? (result) 0 pc (pc) + 2 + rel ? (result) 0 pc (pc) + 3 + rel ? (result) 0 pc (pc) + 2 + rel ? (result) 0 pc (pc) + 4 + rel ? (result) 0 ?????? dir inh inh ix1 ix sp1 3b 4b 5b 6b 7b 9e6b dd rr rr rr ff rr rr ff rr 5 3 3 5 4 6 dec opr deca decx dec opr ,x dec ,x dec opr ,sp decrement m (m) ? 1 a (a) ? 1 x (x) ? 1 m (m) ? 1 m (m) ? 1 m (m) ? 1 ?? ? dir inh inh ix1 ix sp1 3a 4a 5a 6a 7a 9e6a dd ff ff 4 1 1 4 3 5 div divide a (h:a)/(x) h remainder ???? inh 52 7 eor # opr eor opr eor opr eor opr ,x eor opr ,x eor ,x eor opr ,sp eor opr ,sp exclusive or m with a a (a m) 0?? ? imm dir ext ix2 ix1 ix sp1 sp2 a8 b8 c8 d8 e8 f8 9ee8 9ed8 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 inc opr inca incx inc opr ,x inc ,x inc opr ,sp increment m (m) + 1 a (a) + 1 x (x) + 1 m (m) + 1 m (m) + 1 m (m) + 1 ?? ? dir inh inh ix1 ix sp1 3c 4c 5c 6c 7c 9e6c dd ff ff 4 1 1 4 3 5 jmp opr jmp opr jmp opr ,x jmp opr ,x jmp ,x jump pc jump address ?????? dir ext ix2 ix1 ix bc cc dc ec fc dd hh ll ee ff ff 2 3 4 3 2 jsr opr jsr opr jsr opr ,x jsr opr ,x jsr ,x jump to subroutine pc (pc) + n ( n = 1, 2, or 3) push (pcl); sp (sp) ? 1 push (pch); sp (sp) ? 1 pc unconditional address ?????? dir ext ix2 ix1 ix bd cd dd ed fd dd hh ll ee ff ff 4 5 6 5 4 lda # opr lda opr lda opr lda opr ,x lda opr ,x lda ,x lda opr ,sp lda opr ,sp load a from m a (m) 0?? ? imm dir ext ix2 ix1 ix sp1 sp2 a6 b6 c6 d6 e6 f6 9ee6 9ed6 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 table 7-1. instruction set summary (sheet 4 of 7) source form operation description effect on ccr address mode opcode operand cycles vh i nzc central processor unit (cpu) instruction set summary mc68hc908ql family data sheet motorola central processor unit (cpu) 81 ldhx # opr ldhx opr load h:x from m h:x ( m:m + 1 ) 0?? ? imm dir 45 55 ii jj dd 3 4 ldx # opr ldx opr ldx opr ldx opr ,x ldx opr ,x ldx ,x ldx opr ,sp ldx opr ,sp load x from m x (m) 0?? ? imm dir ext ix2 ix1 ix sp1 sp2 ae be ce de ee fe 9eee 9ede ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 lsl opr lsla lslx lsl opr ,x lsl ,x lsl opr ,sp logical shift left (same as asl) ?? dir inh inh ix1 ix sp1 38 48 58 68 78 9e68 dd ff ff 4 1 1 4 3 5 lsr opr lsra lsr x lsr opr ,x lsr ,x lsr opr ,sp logical shift right ??0 dir inh inh ix1 ix sp1 34 44 54 64 74 9e64 dd ff ff 4 1 1 4 3 5 mov opr,opr mov opr, x+ mov # opr,opr mov x+ ,opr move (m) destination (m) source h:x (h:x) + 1 (ix+d, dix+) 0?? ? dd dix+ imd ix+d 4e 5e 6e 7e dd dd dd ii dd dd 5 4 4 4 mul unsigned multiply x:a (x) (a) ?0???0inh 42 5 neg opr nega negx neg opr ,x neg ,x neg opr ,sp negate (two?s complement) m ?(m) = $00 ? (m) a ?(a) = $00 ? (a) x ?(x) = $00 ? (x) m ?(m) = $00 ? (m) m ?(m) = $00 ? (m) ?? dir inh inh ix1 ix sp1 30 40 50 60 70 9e60 dd ff ff 4 1 1 4 3 5 nop no operation none ??????inh 9d 1 nsa nibble swap a a (a[3:0]:a[7:4]) ??????inh 62 3 ora # opr ora opr ora opr ora opr ,x ora opr ,x ora ,x ora opr ,sp ora opr ,sp inclusive or a and m a (a) | (m) 0 ? ? ? imm dir ext ix2 ix1 ix sp1 sp2 aa ba ca da ea fa 9eea 9eda ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 psha push a onto stack push (a); sp (sp ) ? 1 ??????inh 87 2 pshh push h onto stack push (h) ; sp (sp ) ? 1 ??????inh 8b 2 pshx push x onto stack push (x) ; sp (sp ) ? 1 ??????inh 89 2 pula pull a from stack sp (sp + 1); pull ( a ) ??????inh 86 2 pulh pull h from stack sp (sp + 1); pull ( h ) ??????inh 8a 2 pulx pull x from stack sp (sp + 1); pull ( x ) ??????inh 88 2 table 7-1. instruction set summary (sheet 5 of 7) source form operation description effect on ccr address mode opcode operand cycles vh i nzc c b0 b7 0 b0 b7 c 0 central processor unit (cpu) data sheet mc68hc908ql family 82 central processor unit (cpu) motorola rol opr rola rolx rol opr ,x rol ,x rol opr ,sp rotate left through carry ?? dir inh inh ix1 ix sp1 39 49 59 69 79 9e69 dd ff ff 4 1 1 4 3 5 ror opr rora rorx ror opr ,x ror ,x ror opr ,sp rotate right through carry ?? dir inh inh ix1 ix sp1 36 46 56 66 76 9e66 dd ff ff 4 1 1 4 3 5 rsp reset stack pointer sp $ff ??????inh 9c 1 rti return from interrupt sp (sp) + 1; pull (ccr) sp (sp) + 1; pull (a) sp (sp) + 1; pull (x) sp (sp) + 1; pull (pch) sp (sp) + 1; pull (pcl) inh 80 7 rts return from subroutine sp sp + 1 ; pull ( pch) sp sp + 1; pull (pcl) ??????inh 81 4 sbc # opr sbc opr sbc opr sbc opr ,x sbc opr ,x sbc ,x sbc opr ,sp sbc opr ,sp subtract with carry a (a) ? (m) ? (c) ?? imm dir ext ix2 ix1 ix sp1 sp2 a2 b2 c2 d2 e2 f2 9ee2 9ed2 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 sec set carry bit c 1 ?????1inh 99 1 sei set interrupt mask i 1 ??1???inh 9b 2 sta opr sta opr sta opr ,x sta opr ,x sta ,x sta opr ,sp sta opr ,sp store a in m m (a) 0?? ? dir ext ix2 ix1 ix sp1 sp2 b7 c7 d7 e7 f7 9ee7 9ed7 dd hh ll ee ff ff ff ee ff 3 4 4 3 2 4 5 sthx opr store h:x in m (m:m + 1) (h:x) 0 ? ? ? dir 35 dd 4 stop enable irq pin; stop oscillator i 0; stop oscillator ??0???inh 8e 1 stx opr stx opr stx opr ,x stx opr ,x stx ,x stx opr ,sp stx opr ,sp store x in m m (x) 0?? ? dir ext ix2 ix1 ix sp1 sp2 bf cf df ef ff 9eef 9edf dd hh ll ee ff ff ff ee ff 3 4 4 3 2 4 5 sub # opr sub opr sub opr sub opr ,x sub opr ,x sub ,x sub opr ,sp sub opr ,sp subtract a (a) ? (m) ?? imm dir ext ix2 ix1 ix sp1 sp2 a0 b0 c0 d0 e0 f0 9ee0 9ed0 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 table 7-1. instruction set summary (sheet 6 of 7) source form operation description effect on ccr address mode opcode operand cycles vh i nzc c b0 b7 b0 b7 c central processor unit (cpu) opcode map mc68hc908ql family data sheet motorola central processor unit (cpu) 83 7.8 opcode map see table 7-2 . swi software interrupt pc (pc) + 1; push (pcl) sp (sp) ? 1; push (pch) sp (sp) ? 1; push (x) sp (sp) ? 1; push (a) sp (sp) ? 1; push (ccr) sp (sp) ? 1; i 1 pch interrupt vector high byte pcl interrupt vector low byte ??1???inh 83 9 tap transfer a to ccr ccr (a) inh 84 2 tax transfer a to x x (a) ??????inh 97 1 tpa transfer ccr to a a (ccr) ??????inh 85 1 tst opr tsta tstx tst opr ,x tst ,x tst opr ,sp test for negative or zero (a) ? $00 or (x) ? $00 or (m) ? $00 0 ? ? ? dir inh inh ix1 ix sp1 3d 4d 5d 6d 7d 9e6d dd ff ff 3 1 1 3 2 4 tsx transfer sp to h:x h:x (sp) + 1 ??????inh 95 2 txa transfer x to a a (x) ??????inh 9f 1 txs transfer h:x to sp (sp) (h:x) ? 1 ??????inh 94 2 a accumulator n any bit c carry/borrow bit opr operand (one or two bytes) ccr condition code register pc program counter dd direct address of operand pch program counter high byte dd rr direct address of operand and relative offset of branch instruction pcl program counter low byte dd direct to direct addressing mode rel relative addressing mode dir direct addressing mode rel relative program counter offset byte dix+ direct to indexed with pos t increment addressing mode rr relati ve program counter offset byte ee ff high and low bytes of offset in indexed, 16-bit offs et addressing sp1 stack pointer , 8-bit offset addressing mode ext extended addressing mode sp2 stack pointer 16-bit offset addressing mode ff offset byte in indexed, 8-bit offset addressing sp stack pointer h half-carry bit u undefined h index register high byte v overflow bit hh ll high and low bytes of operand address in extended addressing x index register low byte i interrupt mask z zero bit ii immediate operand byte & logical and imd immediate source to direct des tination addressing mode | logical or imm immediate addressing mode logical exclusive or inh inherent addressing mode ( ) contents of ix indexed, no offset addressing mode ?( ) negation (two?s complement) ix+ indexed, no offset, post increment addressing mode # immediate value ix+d indexed with post increment to direct addressing mode ? sign extend ix1 indexed, 8-bit offset addressing mode loaded with ix1+ indexed, 8-bit offset, pos t increment addressing mode ? if ix2 indexed, 16-bit offset addressing mode : concatenated with m memory location set or cleared n negative bit ? not affected table 7-1. instruction set summary (sheet 7 of 7) source form operation description effect on ccr address mode opcode operand cycles vh i nzc data sheet mc68hc908ql family 84 central processor unit (cpu) motorola central processor unit (cpu) table 7-2. opcode map bit manipulation branch read-modify-write control register/memory dir dir rel dir inh inh ix1 sp1 ix inh inh imm dir ext ix2 sp2 ix1 sp1 ix 0 1 2 3 4 5 6 9e6 7 8 9 a b c d 9ed e 9ee f 0 5 brset0 3dir 4 bset0 2dir 3 bra 2rel 4 neg 2dir 1 nega 1inh 1 negx 1inh 4 neg 2ix1 5 neg 3 sp1 3 neg 1ix 7 rti 1inh 3 bge 2rel 2 sub 2imm 3 sub 2dir 4 sub 3ext 4 sub 3ix2 5 sub 4 sp2 3 sub 2ix1 4 sub 3 sp1 2 sub 1ix 1 5 brclr0 3dir 4 bclr0 2dir 3 brn 2rel 5 cbeq 3dir 4 cbeqa 3imm 4 cbeqx 3imm 5 cbeq 3ix1+ 6 cbeq 4 sp1 4 cbeq 2ix+ 4 rts 1inh 3 blt 2rel 2 cmp 2imm 3 cmp 2dir 4 cmp 3ext 4 cmp 3ix2 5 cmp 4 sp2 3 cmp 2ix1 4 cmp 3 sp1 2 cmp 1ix 2 5 brset1 3dir 4 bset1 2dir 3 bhi 2rel 5 mul 1inh 7 div 1inh 3 nsa 1inh 2 daa 1inh 3 bgt 2rel 2 sbc 2imm 3 sbc 2dir 4 sbc 3ext 4 sbc 3ix2 5 sbc 4 sp2 3 sbc 2ix1 4 sbc 3 sp1 2 sbc 1ix 3 5 brclr1 3dir 4 bclr1 2dir 3 bls 2rel 4 com 2dir 1 coma 1inh 1 comx 1inh 4 com 2ix1 5 com 3 sp1 3 com 1ix 9 swi 1inh 3 ble 2rel 2 cpx 2imm 3 cpx 2dir 4 cpx 3ext 4 cpx 3ix2 5 cpx 4 sp2 3 cpx 2ix1 4 cpx 3 sp1 2 cpx 1ix 4 5 brset2 3dir 4 bset2 2dir 3 bcc 2rel 4 lsr 2dir 1 lsra 1inh 1 lsrx 1inh 4 lsr 2ix1 5 lsr 3 sp1 3 lsr 1ix 2 ta p 1inh 2 txs 1inh 2 and 2imm 3 and 2dir 4 and 3ext 4 and 3ix2 5 and 4 sp2 3 and 2ix1 4 and 3 sp1 2 and 1ix 5 5 brclr2 3dir 4 bclr2 2dir 3 bcs 2rel 4 sthx 2dir 3 ldhx 3imm 4 ldhx 2dir 3 cphx 3imm 4 cphx 2dir 1 tpa 1inh 2 tsx 1inh 2 bit 2imm 3 bit 2dir 4 bit 3ext 4 bit 3ix2 5 bit 4 sp2 3 bit 2ix1 4 bit 3 sp1 2 bit 1ix 6 5 brset3 3dir 4 bset3 2dir 3 bne 2rel 4 ror 2dir 1 rora 1inh 1 rorx 1inh 4 ror 2ix1 5 ror 3 sp1 3 ror 1ix 2 pula 1inh 2 lda 2imm 3 lda 2dir 4 lda 3ext 4 lda 3ix2 5 lda 4 sp2 3 lda 2ix1 4 lda 3 sp1 2 lda 1ix 7 5 brclr3 3dir 4 bclr3 2dir 3 beq 2rel 4 asr 2dir 1 asra 1inh 1 asrx 1inh 4 asr 2ix1 5 asr 3 sp1 3 asr 1ix 2 psha 1inh 1 ta x 1inh 2 ais 2imm 3 sta 2dir 4 sta 3ext 4 sta 3ix2 5 sta 4 sp2 3 sta 2ix1 4 sta 3 sp1 2 sta 1ix 8 5 brset4 3dir 4 bset4 2dir 3 bhcc 2rel 4 lsl 2dir 1 lsla 1inh 1 lslx 1inh 4 lsl 2ix1 5 lsl 3 sp1 3 lsl 1ix 2 pulx 1inh 1 clc 1inh 2 eor 2imm 3 eor 2dir 4 eor 3ext 4 eor 3ix2 5 eor 4 sp2 3 eor 2ix1 4 eor 3 sp1 2 eor 1ix 9 5 brclr4 3dir 4 bclr4 2dir 3 bhcs 2rel 4 rol 2dir 1 rola 1inh 1 rolx 1inh 4 rol 2ix1 5 rol 3 sp1 3 rol 1ix 2 pshx 1inh 1 sec 1inh 2 adc 2imm 3 adc 2dir 4 adc 3ext 4 adc 3ix2 5 adc 4 sp2 3 adc 2ix1 4 adc 3 sp1 2 adc 1ix a 5 brset5 3dir 4 bset5 2dir 3 bpl 2rel 4 dec 2dir 1 deca 1inh 1 decx 1inh 4 dec 2ix1 5 dec 3 sp1 3 dec 1ix 2 pulh 1inh 2 cli 1inh 2 ora 2imm 3 ora 2dir 4 ora 3ext 4 ora 3ix2 5 ora 4 sp2 3 ora 2ix1 4 ora 3 sp1 2 ora 1ix b 5 brclr5 3dir 4 bclr5 2dir 3 bmi 2rel 5 dbnz 3dir 3 dbnza 2inh 3 dbnzx 2inh 5 dbnz 3ix1 6 dbnz 4 sp1 4 dbnz 2ix 2 pshh 1inh 2 sei 1inh 2 add 2imm 3 add 2dir 4 add 3ext 4 add 3ix2 5 add 4 sp2 3 add 2ix1 4 add 3 sp1 2 add 1ix c 5 brset6 3dir 4 bset6 2dir 3 bmc 2rel 4 inc 2dir 1 inca 1inh 1 incx 1inh 4 inc 2ix1 5 inc 3 sp1 3 inc 1ix 1 clrh 1inh 1 rsp 1inh 2 jmp 2dir 3 jmp 3ext 4 jmp 3ix2 3 jmp 2ix1 2 jmp 1ix d 5 brclr6 3dir 4 bclr6 2dir 3 bms 2rel 3 tst 2dir 1 tsta 1inh 1 tstx 1inh 3 tst 2ix1 4 tst 3 sp1 2 tst 1ix 1 nop 1inh 4 bsr 2rel 4 jsr 2dir 5 jsr 3ext 6 jsr 3ix2 5 jsr 2ix1 4 jsr 1ix e 5 brset7 3dir 4 bset7 2dir 3 bil 2rel 5 mov 3dd 4 mov 2dix+ 4 mov 3imd 4 mov 2ix+d 1 stop 1inh * 2 ldx 2imm 3 ldx 2dir 4 ldx 3ext 4 ldx 3ix2 5 ldx 4 sp2 3 ldx 2ix1 4 ldx 3 sp1 2 ldx 1ix f 5 brclr7 3dir 4 bclr7 2dir 3 bih 2rel 3 clr 2dir 1 clra 1inh 1 clrx 1inh 3 clr 2ix1 4 clr 3 sp1 2 clr 1ix 1 wait 1inh 1 txa 1inh 2 aix 2imm 3 stx 2dir 4 stx 3ext 4 stx 3ix2 5 stx 4 sp2 3 stx 2ix1 4 stx 3 sp1 2 stx 1ix inh inherent rel relative sp1 stack pointer, 8-bit offset imm immediate ix indexed, no offset sp2 stack pointer, 16-bit offset dir direct ix1 indexed, 8-bit offset ix+ indexed, no offset with ext extended ix2 indexed, 16-bit offset post increment dd direct-direct imd immediate-direct ix1+ indexed, 1-byte offset with ix+d indexed-direct dix+ direct-indexed post increment * pre-byte for stack pointer indexed instructions 0 high byte of opcode in hexadecimal low byte of opcode in hexadecimal 0 5 brset0 3dir cycles opcode mnemonic number of bytes / addressing mode msb lsb msb lsb mc68hc908ql family data sheet motorola external interrupt (irq) 85 data sheet ? mc68hc908ql4 family section 8. external interrupt (irq) 8.1 introduction the irq pin (external interrupt), shared wi th pta2 (general purpose input) and keyboard interrupt (kbi), provides a maskable interrupt input. 8.2 features features of the irq module include the following: external interrupt pin, irq irq interrupt control bits hysteresis buffer programmable edge-only or edge and level interrupt sensitivity automatic interrupt acknowledge selectable internal pullup resistor 8.3 functional description irq pin functionality is enabled by setting configuration register 2 (config2) irqen bit accordingly. a zero disables the irq function and irq will assume the other shared functionalities. a one enables the irq function. a logic 0 applied to the external interrupt pin can latch a central processor unit (cpu) interrupt request. figure 8-2 shows the structure of the irq module. interrupt signals on the irq pin are latched into the irq latch. an interrupt latch remains set until one of the following actions occurs: vector fetch ? a vector fetch automatically generates an interrupt acknowledge signal that clears the irq latch. software clear ? software can clear the interrupt latch by writing to the acknowledge bit in the interrupt status and control register (iscr). writing a 1 to the ack bit clears the irq latch. reset ? a reset automatically clears the interrupt latch. the external interrupt pin is falling-edge-triggered and is software- configurable to be either falling-edge or falling-edge and lo w-level triggered. the mode bit in the iscr controls the triggeri ng sensitivity of the irq pin. when the interrupt pin is edge-triggered only, the cpu interrupt request remains set until a vector fetch, software clear, or reset occurs. external interrupt (irq) data sheet mc68hc908ql family 86 external interrupt (irq) motorola figure 8-1. block diagram highlighting irq block and pins rst , irq : pins have internal (about 30 k ? ) pull up pta0, pta1, pta3?pta5: high cu rrent sink and s ource capability pta0?pta5: pins have programmable keyboard interrupt and pull up adc pins only available on mc68hc908ql4 and mc68hc908ql2 pta0/ad0/kbi0 pta1/ad1/tch1/kbi1 pta2/irq /kbi2/tclk pta3/rst /kbi3 pta4/osc2/ad2/kbi4 pta5/osc1/ad3/kbi5 ptb0/tch0 ptb1 ptb2/ad4 ptb3/ad5 ptb4/slcrx ptb5/slctx ptb6 ptb7 power supply keyboard interrupt module clock generator (oscillator) system integration module single interrupt module break module power-on reset module 2-ch 16-bit timer module cop module monitor rom v dd v ss 128 bytes ram mc68hc908ql4 and mc68hc908ql3: 4096 bytes mc68hc908ql2: 2048 bytes user flash pta ddra ptb ddrb slave lin interface controller 6-channel 10-bit adc m68hc08 cpu external interrupt (irq) functional description mc68hc908ql family data sheet motorola external interrupt (irq) 87 figure 8-2. irq module block diagram when the interrupt pin is both falling-edge and low-level triggered, the cpu interrupt request remains set until both of the following occur: vector fetch or software clear return of the interrupt pin to logic 1 the vector fetch or software clear may occur before or after the interrupt pin returns to logic 1. as long as the pin is low, the interrupt request remains pending. a reset will clear the latch and the mode control bit, thereby clearing the interrupt even if the pin stays low. when set, the imask bit in the iscr mask all external interrupt requests. a latched interrupt request is not presented to the in terrupt priority logic unless the imask bit is clear. note: the interrupt mask (i) in the condition c ode register (ccr) masks all interrupt requests, including external interrupt requests. see 13.6 exception control . figure 8-3 provides a summary of the irq i/o register. ack imask dq ck clr irq high interrupt to mode select logic irq ff request v dd mode voltage detect synchro- nizer irqf to cpu for bil/bih instructions vector fetch decoder internal address bus reset v dd internal pullup device irq irqpud addr.register name bit 7654321bit 0 $001d irq status and control register (intscr) see page 89. read:0000irqf0 imask mode write: ack reset:00000000 = unimplemented figure 8-3. irq i/o register summary external interrupt (irq) data sheet mc68hc908ql family 88 external interrupt (irq) motorola 8.4 irq pin a logic 0 on the irq pin can latch an interrupt request into the irq latch. a vector fetch, software clear, or reset clears the irq latch. if the mode bit is set, the irq pin is both falling-edge sensitive and low-level sensitive. with mode set, both of the fo llowing actions must occur to clear irq: vector fetch or software clear ? a vector fetch generates an interrupt acknowledge signal to clear the latch. software may generate the interrupt acknowledge signal by writing a 1 to the ack bit in the interrupt status and control register (iscr). the ack bit is us eful in applications that poll the irq pin and require software to clear the ir q latch. writing to the ack bit prior to leaving an interrupt service routin e can also prevent spurious interrupts due to noise. setting ack does not affect subsequent transitions on the irq pin. a falling edge that occurs after writing to the ack bit latches another interrupt request. if the irq mask bit, imask, is clear, the cpu loads the program counter with the vector address at locations $fffa and $fffb. return of the irq pin to logic 1 ? as long as the irq pin is at logic 0, irq remains active. the vector fetch or software clear and the return of the irq pin to logic 1 may occur in any order. the interrupt request remains pending as long as the irq pin is at logic 0. a reset will clear the latch and the mode control bit, thereby clearing the interrupt even if the pin stays low. if the mode bit is clear, the irq pin is falling-edge sens itive only. with mode clear, a vector fetch or software cl ear immediately clears the irq latch. the irqf bit in the iscr register can be used to check for pending interrupts. the irqf bit is not affected by the imask bit, which makes it useful in applications where polling is preferred. note: when the irq function is enabled in the config2 register, the bih and bil instructions can be used to read the logic level on the irq pin. if the irq function is disabled, these instructio ns will behave as if the irq pin is a logic 1, regardless of the actual level on the pin. conversely, when the irq function is enabled, bit 2 of the port a data register will always read a 0. note: when using the level-sensitive interrupt trigger, avoid false interrupts by masking interrupt requests in the interrupt routine. an internal pullup resistor to v dd is connected to the irq pin; this can be disabled by setting the irqpud bit in the config2 register ($001e). 8.5 irq module during break interrupts the system integration module (sim) c ontrols whether the irq latch can be cleared during the break state. the bcfe bit in the break flag control register (bfcr) enables software to clear the latches during the break state. see section 13. system integration module (sim) . external interrupt (irq) irq status and control register mc68hc908ql family data sheet motorola external interrupt (irq) 89 to allow software to clear the irq latch during a break interrupt, write a 1 to the bcfe bit. if a latch is cleared during the break state, it remains cleared when the mcu exits the break state. to protect the latches during the break state, write a 0 to the bcfe bit. with bcfe at 0 (its default state), writing to the ack bit in the irq status and control register during the break state has no effect on the irq latch. 8.6 irq status an d control register the irq status and control register (iscr) controls and monitors operation of the irq module, see section 5. configuration register (config) . the iscr has the following functions: shows the state of the irq flag clears the irq latch masks irq and interrupt request controls triggering sensitivity of the irq interrupt pin irqf ? irq flag this read-only status bit is high when the irq interrupt is pending. 1 = irq interrupt pending 0 = irq interrupt not pending ack ? irq interrupt request acknowledge bit writing a 1 to this write-only bit clears the irq latch. ack always reads as 0. reset clears ack. imask ? irq interrupt mask bit writing a 1 to this read/write bit disabl es irq interrupt requests. reset clears imask. 1 = irq interrupt requests disabled 0 = irq interrupt requests enabled mode ? irq edge/level select bit this read/write bit controls the triggering sensitivity of the irq pin. reset clears mode. 1 = irq interrupt requests on falling edges and low levels 0 = irq interrupt requests on falling edges only address: $001d bit 7654321bit 0 read:0000irqf imask mode write: ack reset:00000000 = unimplemented figure 8-4. irq status and control register (intscr) external interrupt (irq) data sheet mc68hc908ql family 90 external interrupt (irq) motorola mc68hc908ql family data sheet motorola keyboard inte rrupt module (kbi) 91 data sheet ? mc68hc908ql4 family section 9. keyboard in terrupt module (kbi) 9.1 introduction the keyboard interrupt module (kbi) prov ides six independently maskable external interrupts, which are accessible via the pta0?pta5 pins. 9.2 features features of the keyboard interrupt module include: six keyboard interrupt pins with s eparate keyboard interrupt enable bits and one keyboard interrupt mask software configurable pullup device if in put pin is configured as input port bit programmable edge-only or edge and level interrupt sensitivity exit from low-power modes figure 9-1 provides a summary of the input/output (i/o) registers addr.register name bit 7654321bit 0 $001a keyboard status and control register (kbscr) see page 96. read:0000keyf0 imaskk modek write: ackk reset:00000000 $001b keyboard interrupt enable register (kbier) see page 97. read: 0 awuie kbie5 kbie4 kbie3 kbie2 kbie1 kbie0 write: reset:00000000 = unimplemented figure 9-1. kbi i/o register summary keyboard interrupt module (kbi) data sheet mc68hc908ql family 92 keyboard interrupt module (kbi) motorola figure 9-2. block diagram highlighting kbi block and pins rst , irq : pins have internal (about 30 k ? ) pull up pta0, pta1, pta3?pta5: high current sink and source capability pta0?pta5: pins have programmable keyboard interrupt and pull up adc pins only available on mc68hc908ql4 and mc68hc908ql2 pta0/ad0/kbi0 pta1/ad1/tch1/kbi1 pta2/irq /kbi2/tclk pta3/rst /kbi3 pta4/osc2/ad2/kbi4 pta5/osc1/ad3/kbi5 ptb0/tch0 ptb1 ptb2/ad4 ptb3/ad5 ptb4/slcrx ptb5/slctx ptb6 ptb7 power supply keyboard interrupt module clock generator (oscillator) system integration module single interrupt module break module power-on reset module 2-ch 16-bit timer module cop module monitor rom v dd v ss 128 bytes ram mc68hc908ql4 and mc68hc908ql3: 4096 bytes mc68hc908ql2: 2048 bytes user flash pta ddra ptb ddrb slave lin interface controller 6-channel 10-bit adc m68hc08 cpu keyboard interrupt module (kbi) functional description mc68hc908ql family data sheet motorola keyboard inte rrupt module (kbi) 93 figure 9-3. keyboard interrupt block diagram 9.3 functional description the keyboard interrupt module controls the enabling/disabling of interrupt functions on the six port a pins. thes e six pins can be enabled/disabled independently of each other. 9.3.1 keyboard operation writing to the kbie0?kbie5 bits in the keyboard interrupt enable register (kbier) independently enables or disables each port a pin as a keyboard interrupt pin. enabling a keyboard interrupt pin in port a also enables its internal pullup device irrespective of ptapuex bits in the port a input pullup enable register (see 12.2.3 port a input pullup enable register ). a logic 0 applied to an enabled keyboard interrupt pin latches a keyboard interrupt request. a keyboard interrupt is latched when one or more keyboard interrupt inputs goes low after all were high. the modek bit in the keyboard status and control register controls the triggering mode of the keyboard interrupt. if the keyboard interrupt is edge-sens itive only, a falling edge on a keyboard interrupt input does not latch an interrupt request if another keyboard pin is already low. to prevent losing an interrupt request on one input because another input is still low, software can disable the latter input while it is low. if the keyboard interrupt is falling edge and low-level sensitive, an interrupt request is present as long as any keyboard interrupt input is low. kbie0 kbie5 . . . dq ck clr v dd modek imaskk keyboard interrupt ff vector fetch decoder ackk internal bus reset kbi5 kbi0 synchronizer keyf keyboard interrupt request to pullup enable awuireq (1) to pullup enable 1. for awugen logic refer to figure 4-2. auto wakeup interrupt request generation logic . keyboard interrupt module (kbi) data sheet mc68hc908ql family 94 keyboard interrupt module (kbi) motorola if the modek bit is set, the keyboard interrupt inputs are both falling edge and low-level sensitive, and both of the followi ng actions must occur to clear a keyboard interrupt request: vector fetch or software clear ? a vector fetch generates an interrupt acknowledge signal to clear the interrupt request. software may generate the interrupt acknowledge signal by writing a 1 to the ackk bit in the keyboard status and control register (kbscr). the ackk bit is useful in applications that poll the keyboard interrupt inputs and require software to clear the keyboard interrupt request. writing to the ackk bit prior to leaving an interrupt service routine can also prevent spurious interrupts due to noise. setting ackk does not affect subs equent transitions on the keyboard interrupt inputs. a falling edge that occurs after writing to the ackk bit latches another interrupt request. if the keyboard interrupt mask bit, imaskk, is clear, the central proc essor unit (cpu) loads the program counter with the vector address at locations $ffe0 and $ffe1. return of all enabled keyboard interr upt inputs to logic 1 ? as long as any enabled keyboard interrupt pin is at logic 0, the keyboard interrupt remains set. the auto wakeup interrupt input, awuireq, will be cleared only by writing to ackk bit in kbscr or reset. the vector fetch or software clear and the return of all enabled keyboard interrupt pins to logic 1 may occur in any order. if the modek bit is clear, the keyboard in terrupt pin is falling-edge sensitive only. with modek clear, a vector fetch or software clear immediately clears the keyboard interrupt request. reset clears the keyboard interrupt request and the modek bit, clearing the interrupt request even if a keyboard interrupt input stays at logic 0. the keyboard flag bit (keyf) in the keyboard status and control register can be used to see if a pending interrupt exists . the keyf bit is not affected by the keyboard interrupt mask bit (imaskk) which makes it useful in applications where polling is preferred. to determine the logic level on a keyboard interrupt pin, use the data direction register to configure the pin as an input and then read the data register. note: setting a keyboard interrupt enable bit (kbiex) forces the corresponding keyboard interrupt pin to be an input, overriding the data direction register. however, the data direction register bit must be a 0 for software to read the pin. keyboard interrupt module (kbi) wait mode mc68hc908ql family data sheet motorola keyboard inte rrupt module (kbi) 95 9.3.2 keyboard initialization when a keyboard interrupt pin is enabled, it takes time for the internal pullup to reach a logic 1. therefore a false interrupt can occur as soon as the pin is enabled. to prevent a false interrupt on keyboard initialization: 1. mask keyboard interrupts by setting the imaskk bit in the keyboard status and control register. 2. enable the kbi pins by setting the appropriate kbiex bits in the keyboard interrupt enable register. 3. write to the ackk bit in the keyboard st atus and control register to clear any false interrupts. 4. clear the imaskk bit. an interrupt signal on an edge-triggered pin can be acknowledged immediately after enabling the pin. an interrupt si gnal on an edge- and level-triggered interrupt pin must be acknowledged after a delay that depends on the external load. another way to avoid a false interrupt: 1. configure the keyboard pins as outputs by setting the appropriate ddra bits in the data direction register a. 2. write 1s to the appropriate port a data register bits. 3. enable the kbi pins by setting the appropriate kbiex bits in the keyboard interrupt enable register. 9.4 wait mode the keyboard module remains ac tive in wait mode. cleari ng the imaskk bit in the keyboard status and control register enables keyboard interrupt requests to bring the mcu out of wait mode. 9.5 stop mode the keyboard module remains active in stop mode. clearing the imaskk bit in the keyboard status and control register enables keyboard interrupt requests to bring the mcu out of stop mode. 9.6 keyboard module du ring break interrupts the system integration module (sim) controls whether the keyboard interrupt latch can be cleared during the break state. the bcfe bit in the break flag control register (bfcr) enables software to clear status bits during the break state. to allow software to clear the keyboard interrupt latch during a break interrupt, write a 1 to the bcfe bit. if a latch is cleared during the break state, it remains cleared when the mcu exits the break state. keyboard interrupt module (kbi) data sheet mc68hc908ql family 96 keyboard interrupt module (kbi) motorola to protect the latch during the break state, write a 0 to the bcfe bit. with bcfe at 0 (its default state), writing to the keyboard acknowledge bit (ackk) in the keyboard status and control register during the break state has no effect. 9.7 input/output registers the following i/o registers control and m onitor operation of the keyboard interrupt module: keyboard interrupt status and control register (kbscr) keyboard interrupt enable register (kbier) 9.7.1 keyboard status and control register the keyboard status and control register (kbscr): flags keyboard interrupt requests acknowledges keyboard interrupt requests masks keyboard interrupt requests controls keyboard interrupt triggering sensitivity bits 7?4 ? not used these read-only bits always read as 0s. keyf ? keyboard flag bit this read-only bit is set when a keyboard interrupt is pending on port a or auto wakeup. reset clears the keyf bit. 1 = keyboard interrupt pending 0 = no keyboard interrupt pending ackk ? keyboard acknowledge bit writing a 1 to this write-only bit clears the keyboard interrupt request on port a and auto wakeup logic. ackk always reads as 0. reset clears ackk. imaskk? keyboard interrupt mask bit writing a 1 to this read/write bit prevents the output of the keyboard interrupt mask from generating interrupt requests on port a or auto wakeup. reset clears the imaskk bit. 1 = keyboard interrupt requests masked 0 = keyboard interrupt requests not masked address: $001a bit 7654321bit 0 read:0000keyf0 imaskk modek write: ackk reset:00000000 = unimplemented figure 9-4. keyboard status and control register (kbscr) keyboard interrupt module (kbi) input/output registers mc68hc908ql family data sheet motorola keyboard inte rrupt module (kbi) 97 modek ? keyboard triggering sensitivity bit this read/write bit controls the triggering sensitivity of the keyboard interrupt pins on port a and auto wakeup. reset clears modek. 1 = keyboard interrupt requests on falling edges and low levels 0 = keyboard interrupt requests on falling edges only 9.7.2 keyboard interrupt enable register the port a keyboard interrupt enable regist er (kbier) enables or disables each port a pin or auto wakeup to operate as a keyboard interrupt input. kbie5?kbie0 ? port a keyboard interrupt enable bits each of these read/write bits enables the corresponding keyboard interrupt pin on port a to latch interrupt requests. reset clears the keyboard interrupt enable register. 1 = kbix pin enabled as keyboard interrupt pin 0 = kbix pin not enabled as keyboard interrupt pin note: awuie bit is not used in conjunction with the keyboard interrupt feature. to see a description of this bit, see section 4. auto wakeup module (awu) . address: $001b bit 7654321bit 0 read: 0 awuie kbie5 kbie4 kbie3 kbie2 kbie1 kbie0 write: reset:00000000 = unimplemented figure 9-5. keyboard interrupt enable register (kbier) keyboard interrupt module (kbi) data sheet mc68hc908ql family 98 keyboard interrupt module (kbi) motorola mc68hc908ql family data sheet motorola low-voltage inhibit (lvi) 99 data sheet ? mc68hc908ql4 family section 10. low-volt age inhibit (lvi) 10.1 introduction this section describes the low-voltage inhibit (lvi) module, which monitors the voltage on the v dd pin and can force a reset when the v dd voltage falls below the lvi trip falling voltage, v tripf . 10.2 features features of the lvi module include: programmable lvi reset programmable power consumption selectable lvi trip voltage programmable stop mode operation 10.3 functional description figure 10-1 shows the structure of the lvi module. lvistop, lvipwrd, lvi5or3, and lvirstd are user selectable options found in the configuration register (config1). see section 5. configuration register (config) . figure 10-1. lvi module block diagram low v dd detector lvipwrd stop instruction lvistop lvi reset lviout v dd > lvitrip = 0 v dd lvitrip = 1 from config from config v dd from config lvirstd lvi5or3 from config low-voltage inhibit (lvi) data sheet mc68hc908ql family 100 low-voltage inhibit (lvi) motorola the lvi is enabled out of reset. the lvi module contains a bandgap reference circuit and comparator. clearing the lvi power disable bit, lvipwrd, enables the lvi to monitor v dd voltage. clearing the lvi reset disable bit, lvirstd, enables the lvi module to generate a reset when v dd falls below a voltage, v tripf . setting the lvi enable in stop mode bit, lvistop, enables the lvi to operate in stop mode. setting the lvi 5-v or 3-v trip point bit, lvi5or3, enables the trip point voltage, v tripf , to be configured for 5-v operation. clearing the lvi5or3 bit enables the trip point voltage, v tripf , to be configured for 3-v operation. the actual trip thresholds are specified in 17.5 5-v dc electrical characteristics and 17.9 3.3-v dc electrical characteristics . note: after a power-on reset, the lvi?s default mode of operation is 3 volts. if a 5-v system is used, the user must set the lvi5or3 bit to raise the trip point to 5-v operation. if the user requires 5-v mode and sets t he lvi5or3 bit after power-on reset while the v dd supply is not above the v tripr for 5-v mode, the microcontroller unit (mcu) will immediately go into reset. the next time the lvi releases the reset, the supply will be above the v tripr for 5-v mode. once an lvi reset o ccurs, the mcu remains in reset until v dd rises above a voltage, v tripr , which causes the mcu to exit reset. see section 13. system integration module (sim) for the reset recovery sequence. the output of the comparator controls the state of the lviout flag in the lvi status register (lvisr) and can be used for polling lvi operation when the lvi reset is disabled. 10.3.1 polled lvi operation in applications that can operate at v dd levels below the v tripf level, software can monitor v dd by polling the lviout bit. in the configuration register, the lvipwrd bit must be at 0 to enable the lvi module, and the lvirstd bit must be at 1 to disable lvi resets. 10.3.2 forced reset operation in applications that require v dd to remain above the v tripf level, enabling lvi resets allows the lvi module to reset the mcu when v dd falls below the v tripf level. in the configuration register, the lvipwrd and lvirstd bits must be at 0 to enable the lvi module and to enable lvi resets. 10.3.3 voltage hysteresis protection once the lvi has triggered (by having v dd fall below v tripf ), the lvi will maintain a reset condition until v dd rises above the rising trip point voltage, v tripr . this prevents a condition in which the mcu is co ntinually entering and exiting reset if v dd is approximately equal to v tripf . v tripr is greater than v tripf by the hysteresis voltage, v hys . low-voltage inhibit (lvi) lvi status register mc68hc908ql family data sheet motorola low-voltage inhibit (lvi) 101 10.3.4 lvi trip selection the lvi5or3 bit in the configuration register selects whether the lvi is configured for 5-v or 3-v protection. note: the microcontroller is guaranteed to operate at a minimum supply voltage. the trip point (v tripf [5 v] or v tripf [3 v]) may be lower than this. see 17.5 5-v dc electrical characteristics and 17.9 3.3-v dc electrical characteristics for the actual trip point voltages. 10.4 lvi status register the lvi status register (lvisr) indicates if the v dd voltage was detected below the v tripf level while lvi resets have been disabled . lviout ? lvi output bit this read-only flag becomes set when the v dd voltage falls below the v tripf trip voltage and is cleared when v dd voltage rises above v tripr . the difference in these threshold levels results in a hyst eresis that prevents oscillation into and out of reset (see table 10-1 ). reset clears the lviout bit. address: $fe0c bit 7654321bit 0 read:lviout000000r write: reset:00000000 = unimplemented r = reserved figure 10-2. lvi status register (lvisr) table 10-1. lviout bit indication v dd lviout v dd > v tripr 0 v dd < v tripf 1 v tripf < v dd < v tripr previous value low-voltage inhibit (lvi) data sheet mc68hc908ql family 102 low-voltage inhibit (lvi) motorola 10.5 lvi interrupts the lvi module does not generate interrupt requests. 10.6 low-power modes the stop and wait instructions put the mcu in low power-consumption standby modes. 10.6.1 wait mode if enabled, the lvi module remains active in wait mode. if enabled to generate resets, the lvi module can generate a reset and bring the mcu out of wait mode. 10.6.2 stop mode when the lvipwrd bit in the configurati on register is cleared and the lvistop bit in the configuration register is set, th e lvi module remains active in stop mode. if enabled to generate resets, the lvi module can generate a reset and bring the mcu out of stop mode. mc68hc908ql family data sheet motorola oscillator module (osc) 103 data sheet ? mc68hc908ql4 family section 11. oscillator module (osc) 11.1 introduction the oscillator module is used to pr ovide a stable clock source for the microcontroller system and bus. the os cillator module generates two output clocks, busclkx2 and busclkx4. the bu sclkx4 clock is used by the system integration module (sim) and the computer operating properly module (cop). the busclkx2 clock is divided by two in the sim to be used as the bus clock for the microcontroller. therefore the bus frequency will be one forth of the busclkx4 frequency. 11.2 features the oscillator has these four clock source options available: 1. internal oscillator: an internally gene rated, fixed frequency clock, trimmable to 5%. this is the default option out of reset. 2. external oscillator: an external clock that can be driven directly into osc1. 3. external rc: a built-in oscillator mo dule (rc oscillator) that requires an external r connection only. the capacitor is internal to the chip. 4. external crystal: a built-in oscillator module (xtal oscillator) that requires an external crystal or ceramic-resonator. 11.3 functional description the oscillator contains these major subsystems: internal oscillator circuit internal or external clock switch control external clock circuit external crystal circuit external rc clock circuit oscillator module (osc) data sheet mc68hc908ql family 104 oscillator module (osc) motorola figure 11-1. block diagram highlighting osc block and pins rst , irq : pins have internal (about 30 k ? ) pull up pta0, pta1, pta3?pta5: high current sink and source capability pta0?pta5: pins have programmable keyboard interrupt and pull up adc pins only available on mc68hc908ql4 and mc68hc908ql2 pta0/ad0/kbi0 pta1/ad1/tch1/kbi1 pta2/irq /kbi2/tclk pta3/rst /kbi3 pta4/osc2/ad2/kbi4 pta5/osc1/ad3/kbi5 ptb0/tch0 ptb1 ptb2/ad4 ptb3/ad5 ptb4/slcrx ptb5/slctx ptb6 ptb7 power supply keyboard interrupt module clock generator (oscillator) system integration module single interrupt module break module power-on reset module 2-ch 16-bit timer module cop module monitor rom v dd v ss 128 bytes ram mc68hc908ql4 and mc68hc908ql3: 4096 bytes mc68hc908ql2: 2048 bytes user flash pta ddra ptb ddrb slave lin interface controller 6-channel 10-bit adc m68hc08 cpu oscillator module (osc) functional description mc68hc908ql family data sheet motorola oscillator module (osc) 105 11.3.1 internal oscillator the internal oscillator circuit is designed for use with no external components to provide a clock source with tolerance less than 25% untrimmed. an 8-bit trimming register allows the adjust to a tolerance of less than 5%. the internal oscillator will generate a clock of 25.6 mhz typical (intclk) resulting in a maximum bus speed (internal clock 4) of 6.4 mhz. the bus clock is software selectable to be 3.2 mhz, which is the default frequency after reset. the 3.2 mhz selection is required for applications ru nning at 3.3 v. the maximum frequency at 5 v is 8 mhz, since the internal oscillator will have a 25% tolerance (pre-trim), then the +25% case should not allow a frequency higher than 8 mhz: 6.4 mhz + 25% = 8 mhz for 5 v operation 3.2 mhz + 25% = 4 mhz for 3.3 v operation figure 11-3 shows how busclkx4 is derived from intclk and, like the rc oscillator, osc2 can output busclkx4 by setting osc2en in ptapue register. see section 12. input/output ports (ports) . 11.3.1.1 internal oscillator trimming the 8-bit trimming register, osctrim, a llows a clock period adjust of +127 and ?128 steps. increasing osctrim value increases the clock period. trimming allows the internal clock frequency to be set to 25.6 mhz 5%. there?s an option to order a trimmed version of mc68hc908ql4. the trimming value will be provided in a known flash location, $ffc0. so that the user would be able to copy this byte from the flash to the osctrim register right at the beginning of assembly code. reset loads osctrim with a default value of $80. 11.3.1.2 internal to external clock switching when external clock source (external osc, rc, or xtal) is desired, the user must perform the following steps: 1. for external crystal circuits only, oscopt[1:0] = 1:1: to help precharge an external crystal oscillator, set pta4 (osc2) as an output and drive high for several cycles. this may help the cr ystal circuit start more robustly. 2. set config2 bits osco pt[1:0] according to table 11-2 . the oscillator module control logic will then set osc1 as an external clock input and, if the external crystal option is selected, osc2 will also be set as the clock output. 3. create a software delay to wait the stabilization time needed for the selected clock source (crystal, resonator, rc ) as recommended by the component manufacturer. a good rule of thumb for crystal oscillators is to wait 4096 cycles of the crystal frequency, i.e., for a 4-mhz crystal, wait approximately 1 ms. oscillator module (osc) data sheet mc68hc908ql family 106 oscillator module (osc) motorola 4. after the manufacturer?s recommended delay has elapsed, the ecgon bit in the osc status register (oscstat) needs to be set by the user software. 5. after ecgon set is detected, the osc module checks for o scillator activity by waiting two external clock rising edges. 6. the osc module then switches to the ex ternal clock. logic provides a glitch free transition. 7. the osc module first sets the ecgst bit in the oscstat register and then stops the internal oscillator. note: once transition to the external clock is done, the internal oscillator will only be reactivated with reset. no post-switch cloc k monitor feature is implemented (clock does not switch back to internal if external clock dies). 11.3.2 external oscillator the external clock option is designed for us e when a clock signal is available in the application to provide a clock source to the microcontroller. the osc1 pin is enabled as an input by the oscillator modul e. the clock signal is used directly to create busclkx4 and also divided by two to create busclkx2. in this configuration, the osc2 pin cannot output busclkx4. so the osc2en bit in the port a pullup enable register will be clear to enable pta4 i/o functions on the pin. 11.3.3 xtal oscillator the xtal oscillator circuit is designed for use with an external crystal or ceramic resonator to provide an accurate clock source. in this configuration, the osc2 pin is dedicated to the external crystal circ uit. the osc2en bit in the port a pullup enable register has no effect when this clock mode is selected. in its typical configuration, the xtal osci llator is connected in a pierce oscillator configuration, as shown in figure 11-2 . this figure shows only the logical representation of the internal components and may not represent actual circuitry. the oscillator configuration uses five components: crystal, x 1 fixed capacitor, c 1 tuning capacitor, c 2 (can also be a fixed capacitor) feedback resistor, r b series resistor, r s (optional) note: the series resistor (r s ) is included in the diagram to follow strict pierce oscillator guidelines and may not be required for all ranges of operation, especially with high frequency crystals. refer to the crystal m anufacturer?s data for more information. oscillator module (osc) oscillator module signals mc68hc908ql family data sheet motorola oscillator module (osc) 107 figure 11-2. xtal oscillator external connections 11.3.4 rc oscillator the rc oscillator circuit is designed for use with external r to provide a clock source with tolerance less than 25%. in its typical configuration, the rc oscillator requires two external components, one r and one c. in the mc68hc908ql4, the capacitor is internal to the chip. the r value should have a tolerance of 1% or less, to obtain a clock source with less than 25% tolerance. the oscillator configuration uses one component, r ext . in this configuration, the osc2 pin can be left in the reset state as pta4. or, the osc2en bit in the port a pullup enable register can be set to enable the osc2 output function on the pin. enabling the osc2 output slightly increases the external rc oscillator frequency, f rcclk . see figure 11-3 . 11.4 oscillator module signals the following paragraphs describe the signal s that are inputs to and outputs from the oscillator module. 11.4.1 crystal amplifier input pin (osc1) the osc1 pin is either an input to the crystal oscillator amplifier, an input to the rc oscillator circuit, or an external clock source. for the internal oscillator configuration, the osc1 pin can assume other functions according to table 1-3. function priority in shared pins . c 1 c 2 simoscen xtalclk r b x 1 r s (1) mcu from sim osc2 osc1 2 busclkx2 busclkx4 to sim to sim note 1. r s can be zero (shorted) when used with higher-frequency crystals. refer to manufacturer?s data. see section 17. electrical specifications for component value requirements. oscillator module (osc) data sheet mc68hc908ql family 108 oscillator module (osc) motorola figure 11-3. rc oscillator external connections 11.4.2 crystal amplifier output pin (osc2/pta4/busclkx4) for the xtal oscillator device , the osc2 pin is the cr ystal oscillator inverting amplifier output. for the external clock option, the osc2 pin is dedicated to the pta4 i/o function. the osc2en bit has no effect. for the internal oscillator or rc oscillat or options, the osc2 pin can assume other functions according to table 1-3. function priority in shared pins , or the output of the oscillator clock (busclkx4). mcu r ext simoscen osc1 external rc oscillator en rcclk 2 busclkx2 busclkx4 to sim from sim v dd pta4 i/o 1 0 pta4 osc2en pta4/busclkx4 (osc2) to sim see section 17. electr ical specifications for component value requirements. 0 1 intclk oscrcopt table 11-1. osc2 pin function option osc2 pin function xtal oscillator inverting osc1 external clock pta4 i/o internal oscillator or rc oscillator controlled by osc2en bit in ptapue register osc2en = 0: pta4 i/o osc2en = 1: busclkx4 output oscillator module (osc) oscillator module signals mc68hc908ql family data sheet motorola oscillator module (osc) 109 11.4.3 oscillator enable signal (simoscen) the simoscen signal comes from the system integration module (sim) and enables/disables either the xtal oscillator circuit, the rc oscillator, or the internal oscillator. 11.4.4 xtal oscillator clock (xtalclk) xtalclk is the xtal oscillator output signal. it runs at the full speed of the crystal (f xclk ) and comes directly from the crystal oscillator circuit. figure 11-2 shows only the logical relation of xtalclk to osc1 and osc2 and may not represent the actual circuitry. the duty cycle of xtalclk is unknown and may depend on the crystal and other external factors. also, the frequency and amplitude of xtalclk can be unstable at start up. 11.4.5 rc oscillator clock (rcclk) rcclk is the rc oscillator output signal. its frequency is directly proportional to the time constant of external r and internal c. figure 11-3 shows only the logical relation of rcclk to osc1 and may not represent the actual circuitry. 11.4.6 internal oscillator clock (intclk) intclk is the internal oscillator output signal. intclk is software selectable to be 12.8 mhz or 25.6 mhz, but it can also trimmed using the oscillator trimming feature of the osctrim register (see 11.3.1.1 internal oscillator trimming ). 11.4.7 oscillator out 2 (busclkx4) busclkx4 is the same as the input cl ock (xtalclk, rcclk, or intclk). this signal is driven to the sim module and is used to determine the cop cycles. 11.4.8 oscillator out (busclkx2) the frequency of this signal is equal to hal f of the busclkx4, this signal is driven to the sim for generation of the bus clocks used by the cpu and other modules on the mcu. busclkx2 will be divided again in the sim and results in the internal bus frequency being one fourth of either the xtalclk, rcclk, or intclk frequency. oscillator module (osc) data sheet mc68hc908ql family 110 oscillator module (osc) motorola 11.5 low power modes the wait and stop instructions put the mcu in low-power consumption standby modes. 11.5.1 wait mode the wait instruction has no effect on the oscillator logic. busclkx2 and busclkx4 continue to drive to the sim module. 11.5.2 stop mode the stop instruction disables either the xtalclk, the rcclk, or intclk output, hence busclkx2 and busclkx4. 11.6 oscillator during break mode the oscillator continues to drive busclkx2 and busclkx4 when the device enters the break state. 11.7 config2 options two config2 register options affect the operation of the oscillator module: oscopt1 and oscopt0. all config2 r egister bits will have a default configuration. refer to section 5. configuration register (config) for more information on how the config2 register is used. table 11-2 shows how the oscopt bits are used to select the oscillator clock source. table 11-2. oscillator modes oscopt1 oscopt0 oscillator modes 0 0 internal oscillator 0 1 external oscillator 10external rc 1 1 external crystal oscillator module (osc) input/output (i/o) registers mc68hc908ql family data sheet motorola oscillator module (osc) 111 11.8 input/output (i/o) registers the oscillator module contains these two registers: 1. oscillator status register (oscstat) 2. oscillator trim register (osctrim) 11.8.1 oscillator status register the oscillator status register (oscstat) contains the bits for switching from internal to external clock sources. bfs ? bus frequency select bit this read/write bit enables the bus frequency to be increased for 5-v applications from 3.2 mhz to 6.4 mhz when running off the internal oscillator. 1 = 6.4 mhz bus frequency 0 = 3.2 mhz bus frequency ecgon ? external clock generator on bit this read/write bit enables external clock generator, so that the switching process can be initiated. this bit is forc ed low during reset. this bit is ignored in monitor mode with the internal os cillator bypassed, ptm or ctm mode. 1 = external clock generator enabled 0 = external clock generator disabled ecgst ? external clock status bit this read-only bit indicates whether or not an external clock source is engaged to drive the system clock. 1 = an external clock source engaged 0 = an external clock source disengaged address: $0036 bit 7654321bit 0 read: rrrrrbfsecgon ecgst write: reset:00000000 r =reserved = unimplemented figure 11-4. oscillator status register (oscstat) oscillator module (osc) data sheet mc68hc908ql family 112 oscillator module (osc) motorola 11.8.2 oscillator trim register (osctrim) trim7?trim0 ? internal osc illator trim factor bits these read/write bits change the size of the internal capacitor used by the internal oscillator. by measuring the period of the internal clock and adjusting this factor accordingly, the frequency of the internal clock can be fine tuned. increasing (decreasing) this factor by one increases (decreases) the period by approximately 0.2% of the untrimmed period (the period for trim = $80). the trimmed frequency is guaranteed not to vary by more than 5% over the full specified range of temperature and voltage. the reset value is $80, which sets the frequency to 12.8 mhz (3.2 mhz bus speed, provided bfs = 0) 25%. address: $0038 bit 7654321bit 0 read: trim7 trim6 trim5 trim4 trim3 trim2 trim1 trim0 write: reset:10000000 figure 11-5. oscillator trim register (osctrim) mc68hc908ql family data sheet motorola input/output ports (ports) 113 data sheet ? mc68hc908ql4 family section 12. input/output ports (ports) 12.1 introduction mc68hc908ql4, mc68hc908ql3, mc68hc908ql2, and mc68hc908ql4 have thirteen bidirectional pins and one inpu t only pin. all input/output (i/o) pins are programmable as inputs or outputs. note: connect any unused i/o pins to an appropriate logic level, either v dd or v ss . although the i/o ports do not require termin ation for proper operation, termination reduces excess current consumption and the possibility of electrostatic damage. figure 12-1 provides a summary of the i/o registers. addr.register name bit 7654321bit 0 $0000 port a data register (pta) see page 114. read: 0 awul pta5 pta4 pta3 pta2 pta1 pta0 write: reset: unaffected by reset $0001 port b data register (ptb) see page 117. read: ptb7 ptb6 ptb5 ptb4 ptb3 ptb2 ptb1 ptb0 write: reset: unaffected by reset $0004 data direction register a (ddra) see page 115. read: 0 0 ddra5 ddra4 ddra3 0 ddra1 ddra0 write: reset:00000000 $0005 data direction register b (ddrb) see page 117. read: ddrb7 ddrb6 ddrb5 ddrb4 ddrb3 ddrb2 ddrb1 ddrb0 write: reset:00000000 $000b port a input pullup enable register (ptapue) see page 116. read: osc2en ptapue5 ptapue4 ptapue3 ptapue2 ptapue1 ptapue0 write: reset:00000000 $000c port b input pullup enable register (ptbpue) see page 119. read: ptbpue7 ptbpue6 ptbpue5 ptbpue4 ptbpue3 ptbpue2 ptbpue1 ptbpue0 write: reset:00000000 = unimplemented figure 12-1. i/o port register summary input/output ports (ports) data sheet mc68hc908ql family 114 input/output ports (ports) motorola 12.2 port a port a is an 6-bit special function port that shares all six of its pins with the keyboard interrupt (kbi) module (see section 9. keyboard interrupt module (kbi) ). each port a pin also has a software configurabl e pullup device if the corresponding port pin is configured as an input port. note: pta2 is input only. pta0, pta1, pta4, and pta5 can also serve as esci pins when the irq function is enabled in the configuration register 2 (config2), bit 2 of the port a data register (pta) will always read a 0. in this case, the bih and bil instructions can be used to read the logic level on the pta2 pin. when the irq function is disabled, these in structions will behave as if the pta2 pin is a logic 1. however, reading bit 2 of pta will read the actual logic level on the pin. 12.2.1 port a data register the port a data register (pta) contains a da ta latch for each of the six port a pins. pta[5:0] ? port a data bits these read/write bits are software progra mmable. data direction of each port a pin is under the control of the corresponding bit in data direction register a. reset has no effect on port a data. awul ? auto wakeup latch data bit this is a read-only bit which has the va lue of the auto wakeup interrupt request latch. the wakeup request signal is generated internally. there is no pta6 port nor any of the associated bits such as pta6 data register, pullup enable or direction. see section 4. auto wakeup module (awu) kbi[5:0] ? port a keyboard interrupts the keyboard interrupt enable bits, kbie5?kbie0, in the keyboard interrupt control enable register (kbier) enable the port a pins as external interrupt pins. see section 9. keyboard interrupt module (kbi) . address: $0000 bit 7654321bit 0 read: 0 awul pta5 pta4 pta3 pta2 pta1 pta0 write: reset: unaffected by reset additional functions: kbi5 kbi4 kbi3 kbi2 kbi1 kbi0 = unimplemented figure 12-2. port a data register (pta) input/output ports (ports) port a mc68hc908ql family data sheet motorola input/output ports (ports) 115 12.2.2 data direction register a data direction register a (ddra) determines whether each port a pin is an input or an output. writing a 1 to a ddra bit enab les the output buffer for the corresponding port a pin; a 0 disables the output buffer. ddra[5:0] ? data direction register a bits these read/write bits control port a data direction. reset clears ddra[5:0], configuring all port a pins as inputs. 1 = corresponding port a pin configured as output 0 = corresponding port a pin configured as input note: avoid glitches on port a pins by writing to the port a data register before changing data direction register a bits from 0 to 1. figure 12-4 shows the port a i/o logic. figure 12-4. port a i/o circuit note: figure 12-4 does not apply to pta2 when ddrax is a 1, reading address $0000 reads the ptax data latch. when ddrax is a 0, reading address $0000 reads the voltage level on the pin. the data latch can always be written, regardless of the state of its data direction bit. address: $0004 bit 7654321bit 0 read: 0 0 ddra5 ddra4 ddra3 0 ddra1 ddra0 write: reset:00000000 = unimplemented figure 12-3. data direction register a (ddra) read ddra ($0004) write ddra ($0004) reset write pta ($0000) read pta ($0000) ptax ddrax ptax internal data bus 30 k ptapuex to keyboard interrupt circuit input/output ports (ports) data sheet mc68hc908ql family 116 input/output ports (ports) motorola 12.2.3 port a input pullup enable register the port a input pullup enable register (ptapue) contains a software configurable pullup device for each if the six port a pins . each bit is individually configurable and requires the corresponding data direction register, ddrax, to be configured as input. each pullup device is automatically and dynamically disabled when its corresponding ddrax bit is configured as output. osc2en ? enable pta4 on osc2 pin this read/write bit configures the osc2 pin function when internal oscillator or rc oscillator option is selected. this bit has no effect for the xtal or external oscillator options. 1 = osc2 pin outputs the internal or rc oscillator clock (busclkx4) 0 = osc2 pin configured for pta4 i/o, having all the interrupt and pullup functions ptapue[5:0] ? port a input pullup enable bits these read/write bits are software pr ogrammable to enable pullup devices on port a pins. 1 = corresponding port a pin configured to have internal pull if its ddra bit is set to 0 0 = pullup device is disconnected on t he corresponding port a pin regardless of the state of its ddra bit table 12-1 summarizes the operation of the port a pins. address: $000b bit 7654321bit 0 read: osc2en ptapue5 ptapue4 ptapue3 ptapue2 ptapue2 ptapue0 write: reset:00000000 = unimplemented figure 12-5. port a input pullup enable register (ptapue) table 12-1. port a pin functions ptapue bit ddra bit pta bit i/o pin mode accesses to ddra accesses to pta read/write read write 10 x (1) input, v dd (2) ddra5?ddra0 pin pta5?pta0 (3) 00x input, hi-z (4) ddra5?ddra0 pin pta5?pta0 (3) x 1 x output ddra5?ddra0 pta5?pta0 pta5?pta0 (5) 1. x = don?t care 2. i/o pin pulled to v dd by internal pullup. 3. writing affects data regist er, but does not affect input. 4. hi-z = high impedance 5. output does not apply to pta2 input/output ports (ports) port b mc68hc908ql family data sheet motorola input/output ports (ports) 117 12.3 port b port b is an 8-bit general purpose i/o port. port b is only available on the mc68hc908ql4, mc68hc908ql3, and mc68hc908ql2. 12.3.1 port b data register the port b data register (ptb) contains a data latch for each of the eight port b pins. ptb[7:0] ? port b data bits these read/write bits are software progra mmable. data direction of each port b pin is under the control of the corresponding bit in data direction register b. reset has no effect on port b data. 12.3.2 data direction register b data direction register b (ddrb) determines whether each port b pin is an input or an output. writing a 1 to a ddrb bit enab les the output buffer for the corresponding port b pin; a 0 disables the output buffer. ddrb[7:0] ? data direction register b bits these read/write bits control port b data direction. reset clears ddrb[7:0], configuring all port b pins as inputs. 1 = corresponding port b pin configured as output 0 = corresponding port b pin configured as input note: avoid glitches on port b pins by writing to the port b data register before changing data direction register b bits from 0 to 1. figure 12-8 shows the port b i/o logic. address: $0001 bit 7654321bit 0 read: ptb7 ptb6 ptb5 ptb4 ptb3 ptb2 ptb1 ptb0 write: reset: unaffected by reset figure 12-6. port b data register (ptb) address: $0005 bit 7654321bit 0 read: ddrb7 ddrb6 ddrb5 ddrb4 ddrb3 ddrb2 ddrb1 ddrb0 write: reset:00000000 figure 12-7. data direction register b (ddrb) input/output ports (ports) data sheet mc68hc908ql family 118 input/output ports (ports) motorola figure 12-8. port b i/o circuit when ddrbx is a 1, reading address $0001 reads the ptbx data latch. when ddrbx is a 0, reading address $0001 reads the voltage level on the pin. the data latch can always be written, regardless of the state of its data direction bit. table 12-2 summarizes the operation of the port b pins. table 12-2. port b pin functions ddrb bit ptb bit i/o pin mode accesses to ddrb accesses to ptb read/write read write 0 x (1) 1. x = don?t care input, hi-z (2) 2. hi-z = high impedance ddrb7?ddrb0 pin ptb7?ptb0 (3) 3. writing affects data register, but does not affect the input. 1 x output ddrb7?ddrb0 pin ptb7?ptb0 read ddrb ($0005) write ddrb ($0005) reset write ptb ($0001) read ptb ($0001) ptbx ddrbx ptbx internal data bus 30 k ptbpuex input/output ports (ports) port b mc68hc908ql family data sheet motorola input/output ports (ports) 119 12.3.3 port b input pullup enable register the port b input pullup enable register (ptbpue) contains a software configurable pullup device for each of the eight port b pins. each bit is individually configurable and requires the corresponding data direction register, ddrbx, be configured as input. each pullup device is automatically and dynamically disabled when its corresponding ddrbx bit is configured as output. ptbpue[7:0] ? port b input pullup enable bits these read/write bits are software pr ogrammable to enable pullup devices on port b pins 1 = corresponding port b pin configured to have internal pull if its ddrb bit is set to 0 0 = pullup device is disconnected on t he corresponding port b pin regardless of the state of its ddrb bit. table 12-3 summarizes the operation of the port b pins. address: $000c bit 7654321bit 0 read: ptbpue7 ptbpue6 ptbpue5 ptbpue4 ptbpue3 ptbpue2 ptbpue2 ptbpue0 write: reset:00000000 figure 12-9. port b input pullup enable register (ptbpue) table 12-3. port b pin functions ptbpue bit ddrb bit ptb bit i/o pin mode accesses to ddrb accesses to ptb read/write read write 10 x (1) input, v dd (2) ddrb7?ddrb0 pin ptb7?ptb0 (3) 00x input, hi-z (4) ddrb7?ddrb0 pin ptb7?ptb0 (3) x 1 x output ddrb7?ddrb0 ptb7?ptb0 ptb7?ptb0 1. x = don?t care 2. i/o pin pulled to v dd by internal pullup. 3. writing affects data regist er, but does not affect input. 4. hi-z = high impedance input/output ports (ports) data sheet mc68hc908ql family 120 input/output ports (ports) motorola mc68hc908ql family data sheet motorola system integr ation module (sim) 121 data sheet ? mc68hc908ql4 family section 13. system inte gration module (sim) 13.1 introduction this section describes the system integr ation module (sim), which supports up to 24 external and/or internal interrupts. together with the central processor unit (cpu), the sim controls all microcontrolle r unit (mcu) activities. a block diagram of the sim is shown in figure 13-1 . figure 13-2 is a summary of the sim i/o registers. the sim is a system state controller that coordinates cpu and exception timing. the sim is responsible for: bus clock generation and control for cpu and peripherals ? stop/wait/reset/break entry and recovery ? internal clock control master reset control, including power-on reset (por) and computer operating properly (cop) timeout interrupt control: ? acknowledge timing ? arbitration control timing ? vector address generation cpu enable/disable timing 13.2 r st and irq pins initialization rst and irq pins come out of reset as pta3 and pta2 respectively. rst and irq functions can be activated by progr aming config2 accordingly. refer to section 5. configuration register (config) . 13.3 sim bus clock co ntrol and generation the bus clock generator provides system clock signals for the cpu and peripherals on the mcu. the system clocks are generated from an incoming clock, busclkx2, as shown in figure 13-3 . system integration module (sim) data sheet mc68hc908ql family 122 system integration module (sim) motorola figure 13-1. sim block diagram stop/wait clock control clock generators por control reset pin control sim reset status register interrupt control and priority decode module stop module wait cpu stop (from cpu) cpu wait (from cpu) simoscen (to oscillator) busclkx2 (from oscillator) internal clocks master reset control reset pin logic illegal opcode (from cpu) illegal address (from address map decoders) cop timeout (from cop module) interrupt sources cpu interface reset control sim counter cop clock busclkx4 (from oscillator) 2 lvi reset (from lvi module) v dd internal pull-up forced mon mode entry (from menrst module) table 13-1. signal name conventions signal name description busclkx4 buffered clock from the internal, rc or xtal oscillator circuit. busclkx2 the busclkx4 frequency divided by two. this signal is again divided by two in the sim to generate the internal bus clocks (bus clock = busclkx4 4). address bus internal address bus data bus internal data bus porrst signal from the power-on reset module to the sim irst internal reset signal r/w read/write signal system integration module (sim) sim bus clock control and generation mc68hc908ql family data sheet motorola system integr ation module (sim) 123 figure 13-3. sim clock signals 13.3.1 bus timing in user mode , the internal bus frequency is t he oscillator frequency (busclkx4) divided by four. addr. register name bit 7 6 5 4 3 2 1 bit 0 $fe00 break status register (bsr) see page 138. read: rrrrrr sbsw r write: note 1 reset:00000000 1. writing a 0 clears sbsw. $fe01 sim reset status register (srsr) see page 137. read: por pin cop ilop ilad modrst lvi 0 write: por:10000000 $fe02 reserved rrrrrrrr $fe03 break flag control register (bfcr) see page 138. read: bcferrrrrrr write: reset: 0 $fe04 interrupt status register 1 (int1) see page 132. read:0if5if4if30if10 0 write:rrrrrrrr reset:00000000 $fe05 interrupt status register 2 (int2) see page 133. read:if140000000 write:rrrrrrrr reset:00000000 $fe06 interrupt status register 3 (int3) see page 133. read:0000000if15 write:rrrrrrrr reset:00000000 = unimplemented r = reserved figure 13-2. sim i/o register summary 2 bus clock generators sim sim counter from oscillator from oscillator busclkx2 busclkx4 system integration module (sim) data sheet mc68hc908ql family 124 system integration module (sim) motorola 13.3.2 clock start-up from por when the power-on reset module generates a reset, the clocks to the cpu and peripherals are inactive and held in an inactive phase until after the 4096 busclkx4 cycle por time out has completed. the ibus clocks start upon completion of the time out. 13.3.3 clocks in stop mode and wait mode upon exit from stop mode by an interrupt or reset, the sim allows busclkx4 to clock the sim counter. the cpu and peripheral clocks do not become active until after the stop delay time out. this time out is selectable as 4096 or 32 busclkx4 cycles. see 13.7.2 stop mode . in wait mode, the cpu clocks are inactive. the sim also produces two sets of clocks for other modules. refer to the wa it mode subsection of each module to see if the module is active or inactive in wait mode. some modules can be programmed to be active in wait mode. 13.4 reset and syst em initialization the mcu has these reset sources: power-on reset module (por) external reset pin (rst ) computer operating properly module (cop) low-voltage inhibit module (lvi) illegal opcode illegal address all of these resets produce the vector $fffe?ffff ($fefe?feff in monitor mode) and assert the internal reset signal (irst). irst causes all registers to be returned to their default values and all modules to be returned to their reset states. an internal reset clears the sim counter (see 13.5 sim counter ), but an external reset does not. each of the resets sets a corresponding bit in the sim reset status register (srsr). see 13.8 sim registers . 13.4.1 external pin reset the rst pin circuits include an internal pullup device. pulling the asynchronous rst pin low halts all processing. the pin bit of the sim reset status register (srsr) is set as long as rst is held low for a minimum of 67 busclkx4 cycles, assuming that the por was not the source of the reset. see table 13-2 for details. figure 13-4 shows the relative timing. the rst pin function is only available if the rsten bit is set in the config1 register. system integration module (sim) reset and system initialization mc68hc908ql family data sheet motorola system integr ation module (sim) 125 figure 13-4. external reset timing 13.4.2 active resets from internal sources the rst pin is initially setup as a general- purpose input after a por. setting the rsten bit in the config1 register enables the pin for the reset function. this section assumes the rsten bit is se t when describing activity on the rst pin. all internal reset sources actively pull the rst pin low for 32 busclkx4 cycles to allow resetting of external peripherals. t he internal reset signal irst continues to be asserted for an additional 32 cycles (see figure 13-5 ). an internal reset can be caused by an illegal address, illegal opcode, cop time out, lvi, or por (see figure 13-6 ). figure 13-5. internal reset timing figure 13-6. sources of internal reset table 13-2. pin bit set timing reset type number of cycles required to set pin por 4163 (4096 + 64 + 3) all others 67 (64 + 3) rst address bus pc vect h vect l busclkx2 irst rst rst pulled low by mcu address 32 cycles 32 cycles vector high busclkx4 bus illegal address rst illegal opcode rst coprst por lvi internal reset system integration module (sim) data sheet mc68hc908ql family 126 system integration module (sim) motorola note: for por resets, the sim cycles through 4096 busclkx4 cycles. the internal reset signal then follows the sequence from the falling edge of rst shown in figure 13-5 . the cop reset is asynchronous to the bus clock. the active reset feature allows the part to issue a reset to peripherals and other chips within a system built around the mcu. 13.4.2.1 power-on reset when power is first applied to the mcu, the power-on reset module (por) generates a pulse to indicate that power on has occurred. sim counter counts out 4096 busclkx4 cycles. sixty-four busclkx4 cycles later, the cpu and memories are released from reset to al low the reset vector sequence to occur. at power on, the following events occur: a por pulse is generated. the internal reset signal is asserted. the sim enables the oscillator to drive busclkx4. internal clocks to the cpu and modules are held inactive for 4096 busclkx4 cycles to allow stabilization of the oscillator. the por bit of the sim reset status register (srsr) is set and all other bits in the register are cleared. see figure 13-7 . figure 13-7. por recovery porrst osc1 busclkx4 busclkx2 rst address bus 4096 cycles 32 cycles 32 cycles $fffe $ffff (rst pin is a general-purpose input after a por) system integration module (sim) sim counter mc68hc908ql family data sheet motorola system integr ation module (sim) 127 13.4.2.2 computer operating properly (cop) reset an input to the sim is reserved for the cop reset signal. the overflow of the cop counter causes an internal reset and sets the cop bit in the sim reset status register (srsr). the sim actively pulls down the rst pin for all internal reset sources. to prevent a cop module time out, write any value to location $ffff. writing to location $ffff clears the cop counter and stages 12?5 of the sim counter. the sim counter output, which occurs at least every (2 12 ? 2 4 ) busclkx4 cycles, drives the cop counter. the cop should be serviced as soon as possible out of reset to guarantee the maximum amount of time before the first time out. the cop module is disabled during a break interrupt with monitor mode when bdcop bit is set in break auxiliary register (brkar). 13.4.2.3 illegal opcode reset the sim decodes signals from the cpu to detect illegal instructions. an illegal instruction sets the ilop bit in the sim reset status register (srsr) and causes a reset. if the stop enable bit, stop, in the mask option register is 0, the sim treats the stop instruction as an illegal opcode and causes an illegal opcode reset. the sim actively pulls down the rst pin for all internal reset sources. 13.4.2.4 illegal address reset an opcode fetch from an unmapped address generates an illegal address reset. the sim verifies that the cpu is fetching an opcode prior to asserting the ilad bit in the sim reset status register (srsr) and resetting the mcu. a data fetch from an unmapped address does not generate a reset. the sim actively pulls down the rst pin for all internal reset sources. 13.4.2.5 low-voltage inhibit (lvi) reset the lvi asserts its output to the sim when the v dd voltage falls to the lvi trip voltage v trip . the lvi bit in the sim reset status register (srsr) is set, and the external reset pin (rst ) is held low while the sim counter counts out 4096 busclkx4 cycles. sixty-four busclkx4 cy cles later, the cpu and memories are released from reset to allow the reset vect or sequence to occur. the sim actively pulls down the (rst ) pin for all internal reset sources. 13.5 sim counter the sim counter is used by the power-on reset module (por) and in stop mode recovery to allow the oscillator time to stabilize before enabling the internal bus (ibus) clocks. the sim counter also serves as a prescaler for the computer system integration module (sim) data sheet mc68hc908ql family 128 system integration module (sim) motorola operating properly module (cop). the sim counter uses 12 stages for counting, followed by a 13th stage that triggers a reset of sim counters and supplies the clock for the cop module. the sim counter is clocked by the falling edge of busclkx4. 13.5.1 sim counter during power-on reset the power-on reset module (por) detects power applied to the mcu. at power-on, the por circuit asserts the signal porrst. once the sim is initialized, it enables the oscillator to driv e the bus clock state machine. 13.5.2 sim counter during stop mode recovery the sim counter also is used for stop mode recovery. the stop instruction clears the sim counter. after an interrupt, break, or reset, the sim senses the state of the short stop recovery bit, ssrec, in the configuration register 1 (config1). if the ssrec bit is a 1, then the stop recovery is reduced from the normal delay of 4096 busclkx4 cycles down to 32 busclkx4 cy cles. this is ideal for applications using canned oscillators that do not requ ire long start-up times from stop mode. external crystal applications should use the full stop recovery time, that is, with ssrec cleared in the configur ation register 1 (config1). 13.5.3 sim counter and reset states external reset has no effect on the sim counter (see 13.7.2 stop mode for details.) the sim counter is free-running after all reset states. see 13.4.2 active resets from internal sources for counter control and internal reset recovery sequences. 13.6 exception control normal sequential program execution c an be changed in three different ways: 1. interrupts a. maskable hardware cpu interrupts b. non-maskable software interrupt instruction (swi) 2. reset 3. break interrupts 13.6.1 interrupts an interrupt temporarily changes the sequen ce of program execution to respond to a particular event. figure 13-8 flow charts the handling of system interrupts. interrupts are latched, and arbitration is performed in the sim at the start of interrupt processing. the arbitration result is a constant that the cpu uses to determine which vector to fetch. once an interrupt is latched by the sim, no other interrupt can take precedence, regardless of priority, until the latched interrupt is serviced (or the i bit is cleared). system integration module (sim) exception control mc68hc908ql family data sheet motorola system integr ation module (sim) 129 figure 13-8. interrupt processing no no no yes no no yes no yes yes (as many interrupts as exist on chip) i bit set? from reset break interrupt? i bit set? irq interrupt? timer interrupt? swi instruction? rti instruction? fetch next instruction unstack cpu registers execute instruction yes yes stack cpu registers set i bit load pc with interrupt vector system integration module (sim) data sheet mc68hc908ql family 130 system integration module (sim) motorola at the beginning of an interrupt, the cpu saves the cpu register contents on the stack and sets the interrupt mask (i bit) to prevent additional interrupts. at the end of an interrupt, the rti instruction recovers the cpu register contents from the stack so that normal processing can resume. figure 13-9 shows interrupt entry timing. figure 13-10 shows interrupt recovery timing. figure 13-9 . interrupt entry figure 13-10. interrupt recovery 13.6.1.1 hardware interrupts a hardware interrupt does not stop the current instruction. processing of a hardware interrupt begins after completion of the current instruction. when the current instruction is complete, the si m checks all pending hardware interrupts. if interrupts are not masked (i bit clear in the condition code register), and if the corresponding interrupt enable bit is set, the sim proceeds with interrupt processing; otherwise, the next instruction is fetched and executed. if more than one interrupt is pending at the end of an instruction execution, the highest priority interrupt is serviced first. figure 13-11 demonstrates what happens when two interrupts are pending. if an interrupt is pending upon exit from the original interrupt service routine, the pending interrupt is serviced before the lda instruction is executed. module data bus r/w interrupt dummy sp sp ? 1 sp ? 2 sp ? 3 sp ? 4 vect h vect l start addr address bus dummy pc ? 1[7:0] pc ? 1[15:8] x a ccr v data h v data l opcode i bit module data bus r/w interrupt sp ? 4 sp ? 3 sp ? 2 sp ? 1 sp pc pc + 1 address bus ccr a x pc ? 1[7:0] pc ? 1[15:8] opcode operand i bit system integration module (sim) exception control mc68hc908ql family data sheet motorola system integr ation module (sim) 131 figure 13-11 . interrupt recognition example the lda opcode is prefetched by both the int1 and int2 return-from-interrupt (rti) instructions. however, in the case of the int1 rti prefetch, this is a redundant operation. note: to maintain compatibility with the m6805 family , the h register is not pushed on the stack during interrupt entry. if the interrupt service routine modifies the h register or uses the indexed addressing m ode, software should save the h register and then restore it prior to exiting the routine. 13.6.1.2 swi instruction the swi instruction is a non-maskable instruction that causes an interrupt regardless of the state of the interrupt mask (i bit) in the condition code register. note: a software interrupt pushes pc onto the stack. a software interrupt does not push pc ? 1, as a hardware interrupt does. cli lda int1 pulh rti int2 background routine #$ff pshh int1 interrupt service routine pulh rti pshh int2 interrupt service routine system integration module (sim) data sheet mc68hc908ql family 132 system integration module (sim) motorola 13.6.2 interrupt status registers the flags in the interrupt status registers identify maskable interrupt sources. table 13-3 summarizes the interrupt sources and the interrupt status register flags that they set. the interrupt status registers can be useful for debugging. 13.6.2.1 interrupt status register 1 if1 and if3?if5 ? interrupt flags these flags indicate the presence of interrupt requests from the sources shown in table 13-3 . 1 = interrupt request present 0 = no interrupt request present bit 0, 1, 3, and 7 ? always read 0 table 13-3. interrupt sources priority source flag mask (1) 1. the i bit in the condition code register is a global mask for all interrupt sources except the swi instruction. int register flag vector address highest lowest reset ? ? ? $fffe?$ffff swi instruction ? ? ? $fffc?$fffd irq pin irqf1 imask1 if1 $fffa?$fffb timer channel 0 interrupt ch0f ch0ie if3 $fff6?$fff7 timer channel 1 interrupt ch1f ch1ie if4 $fff4?$fff5 timer overflow interrupt tof toie if5 $fff2?$fff3 slic interrupt slcf slcie if9 $ffe6?$ffe7 keyboard interrupt keyf imaskk if14 $ffde?$ffdf adc conversion complete interrupt coco aien if15 $ffe0?$ffe1 address: $fe04 bit 7654321bit 0 read: 0 if5 if4 if3 0 if1 0 0 write:rrrrrrrr reset:00000000 r= reserved figure 13-12. interrupt status register 1 (int1) system integration module (sim) exception control mc68hc908ql family data sheet motorola system integr ation module (sim) 133 13.6.2.2 interrupt status register 2 if14 and if11?if9 ? interrupt flags these flags indicate the presence of interrupt requests from the sources shown in table 13-3 . 1 = interrupt request present 0 = no interrupt request present bit 0, 1, 3?6 ? always read 0 13.6.2.3 interrupt status register 3 if15 ? interrupt flags these flags indicate the presence of interrupt requests from the sources shown in table 13-3 . 1 = interrupt request present 0 = no interrupt request present bit 1?7 ? always read 0 13.6.3 reset all reset sources always have equal and highest priority and cannot be arbitrated. 13.6.4 break interrupts the break module can stop normal prog ram flow at a software programmable break point by asserting its break interrupt output. (see section 16. development support .) the sim puts the cpu into the break state by forcing it to the swi vector location. refer to the break interrupt s ubsection of each module to see how each module is affected by the break state. address: $fe05 bit 7654321bit 0 read:if140000if900 write:rrrrrrrr reset:00000000 r= reserved figure 13-13. interrupt status register 2 (int2) address: $fe06 bit 7654321bit 0 read:0000000if15 write:rrrrrrrr reset:00000000 r= reserved figure 13-14. interrupt status register 3 (int3) system integration module (sim) data sheet mc68hc908ql family 134 system integration module (sim) motorola 13.6.5 status flag protection in break mode the sim controls whether status flags co ntained in other modules can be cleared during break mode. the user can select whether flags are protected from being cleared by properly initializing the break clear flag enable bit (bcfe) in the break flag control register (bfcr). protecting flags in break mode ensures that set flags will not be cleared while in break mode. this protection allows registers to be freely read and written during break mode without losing status flag information. setting the bcfe bit enables the clearing mechanisms. once cleared in break mode, a flag remains cleared even when break mode is exited. status flags with a two-step clearing mechanism ? for example, a read of one register followed by the read or write of another ? are protected, even when the first step is accomplished prior to entering break mode. upon leaving break mode, execution of the second step will clear the flag as normal. 13.7 low-power modes executing the wait or stop instruction puts the mcu in a low power-consumption mode for standby situations. the sim holds the cpu in a non-clocked state. the operation of each of these modes is described below. both stop and wait clear the interrupt mask (i) in the condition code register, allowing interrupts to occur. 13.7.1 wait mode in wait mode, the cpu clocks are inacti ve while the peripheral clocks continue to run. figure 13-15 shows the timing for wait mode entry. figure 13-15. wait mode entry timing a module that is active during wait mode can wake up the cpu with an interrupt if the interrupt is enabled. stacking for the interrupt begins one cycle after the wait instruction during which the interrupt occurred. in wait mode, the cpu clocks are inactive. refer to the wait mode subsection of each module to see if the module is active or inactive in wait mode. some modules can be programmed to be active in wait mode. wait addr + 1 same same address bus data bus previous data next opcode same wait addr same r/w note: previous data can be operand data or the wait opcode, depending on the last instruction. system integration module (sim) low-power modes mc68hc908ql family data sheet motorola system integr ation module (sim) 135 wait mode can also be exited by a reset (or break in emulation mode). a break interrupt during wait mode sets the sim break stop/wait bit, sbsw, in the break status register (bsr). if the cop disable bit, copd, in the configuration register is 0, then the computer operating proper ly module (cop) is enabled and remains active in wait mode. figure 13-16 and figure 13-17 show the timing for wait recovery. figure 13-16. wait recovery from interrupt figure 13-17. wait recovery from internal reset 13.7.2 stop mode in stop mode, the sim counter is reset and the system clocks are disabled. an interrupt request from a module can cause an exit from stop mode. stacking for interrupts begins after the selected stop recovery time has elapsed. reset or break also causes an exit from stop mode. the sim disables the oscillator signal s (busclkx2 and busclkx4) in stop mode, stopping the cpu and peripherals. st op recovery time is selectable using the ssrec bit in the configuration register 1 (config1). if ssrec is set, stop recovery is reduced from the normal del ay of 4096 busclkx4 cycles down to 32. this is ideal for the internal oscillator, rc oscillator, and external oscillator options which do not require long start-up times from stop mode. $6e0c $6e0b $00ff $00fe $00fd $00fc $a6 $a6 $01 $0b $6e $a6 address bus data bus exitstopwait note: exitstopwait = rst pin or cpu interrupt address bus data bus rst (1) $a6 $a6 $6e0b rst vct h rst vct l $a6 busclkx4 32 cycles 32 cycles 1. rst is only available if the rsten bi t in the config1 register is set. system integration module (sim) data sheet mc68hc908ql family 136 system integration module (sim) motorola note: external crystal applications should use t he full stop recovery time by clearing the ssrec bit. the sim counter is held in reset from the execution of the stop instruction until the beginning of stop recovery. it is then used to time the recovery period. figure 13-18 shows stop mode entry timing and figure 13-19 shows the stop mode recovery time from interrupt or break note: to minimize stop current, all pins configur ed as inputs should be driven to a logic 1 or logic 0. figure 13-18. stop mode entry timing figure 13-19. stop mode recovery from interrupt 13.8 sim registers the sim has three memory mapped registers. table 13-4 shows the mapping of these registers. stop addr + 1 same same address bus data bus previous data next opcode same stop addr same r/w cpustop note: previous data can be operand data or the stop opcode, depending on the last instruction. busclkx4 interrupt address bus stop + 2 stop + 2 sp sp ? 1 sp ? 2 sp ? 3 stop +1 stop recovery period table 13-4. sim registers address register access mode $fe00 bsr user $fe01 srsr user $fe03 bfcr user system integration module (sim) sim registers mc68hc908ql family data sheet motorola system integr ation module (sim) 137 13.8.1 sim reset status register this register contains seven flags that show the source of the last reset. clear the sim reset status register by reading it. a power-on reset sets the por bit and clears all other bits in the register. por ? power-on reset bit 1 = last reset caused by por circuit 0 = read of srsr pin ? external reset bit 1 = last reset caused by external reset pin (rst ) 0 = por or read of srsr cop ? computer operating properly reset bit 1 = last reset caused by cop counter 0 = por or read of srsr ilop ? illegal opcode reset bit 1 = last reset caused by an illegal opcode 0 = por or read of srsr ilad ? illegal address rese t bit (opcode fetches only) 1 = last reset caused by an opcode fetch from an illegal address 0 = por or read of srsr modrst ? monitor mode entry module reset bit 1 = last reset caused by monitor mode entry when vector locations $fffe and $ffff are $ff after por while irq = v dd 0 = por or read of srsr lvi ? low voltage inhibit reset bit 1 = last reset caused by lvi circuit 0 = por or read of srsr address: $fe01 bit 7654321bit 0 read: por pin cop ilop ilad modrst lvi 0 write: por:10000000 = unimplemented figure 13-20. sim reset status register (srsr) system integration module (sim) data sheet mc68hc908ql family 138 system integration module (sim) motorola 13.8.2 break flag control register the break control register (bfcr) contai ns a bit that enables software to clear status bits while the mcu is in a break state. bcfe ? break clear flag enable bit this read/write bit enables software to clear status bits by accessing status registers while the mcu is in a break state. to clear status bits during the break state, the bcfe bit must be set. 1 = status bits clearable during break 0 = status bits not clearable during break 13.8.3 break status register the break status register (bsr) contains a flag to indicate that a break caused an exit from wait mode. this register is only used in emulation mode. sbsw ? sim break stop/wait sbsw can be read within the break state sw i routine. the user can modify the return address on the stack by subtracting one from it. 1 = wait mode was exited by break interrupt 0 = wait mode was not exited by break interrupt address: $fe03 bit 7654321bit 0 read: bcferrrrrrr write: reset: 0 r = reserved figure 13-21. break flag control register (bfcr) address: $fe00 bit 7654321bit 0 read: rrrrrr sbsw r write: note 1 reset: 0 r = reserved 1. writing a 0 clears sbsw. figure 13-22. break status register (bsr) mc68hc908ql family data sheet motorola slave lin interface controller (slic) 139 data sheet ? mc68hc908ql4 family section 14. slave lin interface controller (slic) 14.1 introduction the slave lin interface controller (slic) is designed to provide slave node connectivity on a local interconnect network (lin) sub-bus. lin is an open-standard serial protocol developed for the automotive industry to connect sensors, motors, and actuators. the slic provides full standard lin message buffering for a slave node, minimizing the need for cpu intervention. routine protocol functions (such as synchronization to the communication channel, reception, and verification of header data) and generation of the checks um are handled automatically by the slic. this allows application software to be greatly simplified relative to standard uart implementations, as well as redu cing the impact of interrupts needed in those applications to handle each byte of a message independently. additionally, the slic has the ability to automatically synchronize to any lin message, regardless of the lin bus bit rate (1?20 kbps), properly receiving that message without prior programming of the target lin bit rate. furthermore, this can even be accomplished using an untrimmed in ternal oscillator, provided it?s accuracy is at least 50% of nominal. the slic also has a simple uart-like byte transfer mode, which allows the user to send and receive single bytes of data in half-duplex 8-n-1 format (8-bit data, no parity, 1 stop bit) without the need for lin message framing. figure 14-2 is a block diagram of the slic module, showing the basic functional blocks contained in the module. slave lin interface controller (slic) data sheet mc68hc908ql family 140 slave lin interface controller (slic) motorola figure 14-1. block diagram highlighting slic block and pins rst , irq : pins have internal (about 30 k ? ) pull up pta0, pta1, pta3?pta5: high cu rrent sink and s ource capability pta0?pta5: pins have programm able keyboard interrupt and pull up adc pins only available on mc68hc908ql4 and mc68hc908ql2 pta0/ad0/kbi0 pta1/ad1/tch1/kbi1 pta2/irq /kbi2/tclk pta3/rst /kbi3 pta4/osc2/ad2/kbi4 pta5/osc1/ad3/kbi5 ptb0/tch0 ptb1 ptb2/ad4 ptb3/ad5 ptb4/slcrx ptb5/slctx ptb6 ptb7 power supply keyboard interrupt module clock generator (oscillator) system integration module single interrupt module break module power-on reset module 2-ch 16-bit timer module cop module monitor rom v dd v ss 128 bytes ram mc68hc908ql4 and mc68hc908ql3: 4096 bytes mc68hc908ql2: 2048 bytes user flash pta ddra ptb ddrb slave lin interface controller 6-channel 10-bit adc m68hc08 cpu slave lin interface controller (slic) features mc68hc908ql family data sheet motorola slave lin interface controller (slic) 141 figure 14-2. slic module block diagram 14.2 features the slic includes these distinctive features: full lin message buffering of identifier and 8 data bytes automatic bit rate and lin message frame synchronization: ? no prior programming of bit rate required, 1?20 kbps lin bus speed operation ? all lin messages will be received (no message loss due to synchronization process) ? input clock tolerance as high as 5 0%, allowing internal oscillator to remain untrimmed ? incoming break symbols always allowed to be 10 or more bit times without message loss ? supports automatic software trimming of internal oscillator using lin synchronization data automatic processing and verification of lin synch break and synch byte status registers control registers bus clock message buffer ? 9 bytes slcid slcd7, slcd6, slcd5, slcd4 shadow register 1 byte lin protocol state machine (psm) digital rx filter slcrx slctx lsvr control lsvr and linif digital rx filter prescaler (rxfp[1:0]) slic clock slcd3, slcd2, slcd1, slcd0 slave lin interface controller (slic) data sheet mc68hc908ql family 142 slave lin interface controller (slic) motorola automatic checksum calculation and verification with error reporting maximum of two interrupts per standard lin message frame with no errors full lin error checking and reporting high-speed lin capability up to 83.33 kbps to 120.00 kbps (1) configurable digital receive filter streamlined interrupt servicing through use of a state vector register switchable uart-like byte transfer mo de for processing bytes one at a time without lin message framing constraints enhanced checksum (includes id) generation and verification 14.3 modes of operation figure 14-3 shows the modes in which the slic will operate. figure 14-3. slic operating modes 1. maximum bit rate of slic module dependent upon frequency of slic input clock. v dd > v dd (min) and any slic reset slic disabled slic run slic init requested slic stop slic wait mcu reset source asserted power off no mcu reset source asserted slce set in slcc2 register network activity or other mcu wakeup (wait instruction and slcwcm = 0) stop instruction (wait instruction and slcwcm = 1) network activity or other mcu wakeup slce cleared in slcc2 register (initack = 1) (from any mode) initreq set to 1 in slcc1 register (from any mode) any mcu reset source asserted v dd <= v dd (min) initreq = 0; (initack = 0) slave lin interface controller (slic) modes of operation mc68hc908ql family data sheet motorola slave lin interface controller (slic) 143 14.3.1 power off this mode is entered from the reset mode whenever the slic module supply voltage v dd drops below its minimum specified value for the slic module to guarantee operation. the slic module w ill be placed in the reset mode by a system low-voltage reset (lvr) before being powered down. in this mode, the pin input and output specifications are not guaranteed. 14.3.2 reset this mode is entered from the power o ff mode whenever the slic module supply voltage v dd rises above its minimum specified value (v dd(min) ) and some mcu reset source is asserted. to prevent the slic from entering an unknown state, the internal mcu reset is asserted while powering up the slic module. slic reset mode is also entered from any other m ode as soon as one of the mcu's possible reset sources (e.g., lvr, por, cop watchdog, rst pin, etc.) is asserted. slic reset mode may also be entered by the user software by asserting the initreq bit. initack indicates whether the slic module is in the reset mode as a result of writing initreq in slcc1. while in the reset state the slic module clocks are stopped. clearing the initreq allows the slic to proceed and enter slic run mode (if slce is set). the module will clear initack once the module has left reset mode and the slic will seek the next lin header. it is the responsibility of the user to verify that this operation is compatible with the application before implementing this feature. in this mode, the internal slic modul e voltage references are operative, v dd is supplied to the internal circuits, which are held in their reset state and the internal slic module system clock is running. registers will assume their reset condition. outputs are held in their programmed reset state, inputs and network activity are ignored. 14.3.3 slic disabled this mode is entered from the reset mode after all mcu reset sources are no longer asserted or initreq bit is cleared by the user and the slic module clears the initack bit. it is entered from the run mode whenever the slce bit in the slcc2 register is cleared. in this mo de the slic clock is stopped to conserve power and allow the slic module to be configured for proper operation on the lin bus. the ip bus interface clocks are left r unning in this mode to allow access to all slic module registers for initialization. slave lin interface controller (slic) data sheet mc68hc908ql family 144 slave lin interface controller (slic) motorola 14.3.4 slic run this mode is entered from the slic di sabled mode when the slce bit in the slcc2 register is set. it is entered from the slic wait mode whenever activity is sensed on the lin bus or some other mcu source wakes the cpu out of wait mode. it is entered from the slic stop mode whenever network activity is sensed or some other mcu source wakes the cpu out of stop mode. messages will not be received properly until the clocks have stabilized and the cpu is also in the run mode. 14.3.5 slic wait (core specific) this power conserving mode is automatical ly entered from the run mode whenever the cpu executes a wait instruction and the slcwcm bit in the slcc1 register is previously cleared. in this mode, the sl ic module internal cloc ks continue to run. any activity on the lin network will cause the slic module to exit slic wait mode and generate an unmaskable interrupt of the cpu. this wakeup interrupt state is reflected in the slcsv, encoded as the highest priority interrupt. this interrupt can be cleared by the cpu with a read of the slcsv. 14.3.6 wakeup from slic wait with cpu in wait if the cpu executes the wait instruction and the slic module enters the wait mode (slcwcm = 0), the clocks to the slic module as well as the clocks in the mcu continue to run. therefore, the message which wakes up the slic module from wait and the cpu from wait mode will also be received correctly by the slic module. this is because all of the requir ed clocks continue to run in the slic module in wait mode. 14.3.7 slic stop (core specific) this power conserving mode is automatical ly entered from the run mode whenever the cpu executes a stop instruction, or if the cpu executes a wait instruction and the slcwcm bit in the slcc1 register is previously set. in this mode, the slic internal clocks are stopped. any activity on the network will cause the slic module to exit slic stop mode and generate an unmaskable interrupt of the cpu. this wakeup interrupt state is reflected in the slcsv, encoded as the highest priority interrupt. this interrupt can be cleared by the cpu with a read of the slcsv. depending upon which low-power mode instruction the cpu executes to cause the slic module to enter slic stop, the me ssage which wakes up the slic module (and the cpu) may or may not be received. slave lin interface controller (slic) modes of operation mc68hc908ql family data sheet motorola slave lin interface controller (slic) 145 there are two different possibilities: 1. wakeup from slic stop with cpu in stop when the cpu executes the stop instruction, all clocks in the mcu, including clocks to the slic module, are turned off. therefore, the message which wakes up the slic module and t he cpu from stop mode will not be received. this is due primarily to the amount of time required for the mcu's oscillator to stabilize before the clocks can be applied internally to the other mcu modules, including the slic module. 2. wakeup from slic stop with cpu in wait if the cpu executes the wait instruction and the slic module enters the stop mode (slcwcm = 1), the clocks to the slic module are turned off, but the clocks in the mcu continue to run. therefore, the message which wakes up the slic module from stop and the cp u from wait mode will be received correctly by the slic module. this is because very little time is required for the cpu to turn the clocks to t he slic module back on once the wakeup interrupt occurs. note: while the slic module will correctly re ceive a message which arrives when the slic module is in stop or wait mode and the mcu is in wait mode, if the user enters this mode while a message is being receiv ed, the data in the message will become corrupted. this is due to the steps required for the slic module to resume operation upon exiting stop or wait mode, and its subsequent resynchronization with the lin bus. 14.3.8 normal and emulation mode operation (core specific) the slic module operates in the same ma nner in all normal and emulation modes. all slic module registers can be read and written except those that are reserved, unimplemented, or write once. the user must be careful not to unintentionally write a register when using 16-bit writes in order to avoid unexpected slic module behavior. 14.3.9 special mode operation (core specific) some aspects of slic module operation can be modified in special test mode. this mode is reserved for internal use only. 14.3.10 low-power options (core specific) the slic module can save power in di sabled, wait, and stop modes. a complete description of what the slic module does while in a low-power mode can be found in 14.3 modes of operation . slave lin interface controller (slic) data sheet mc68hc908ql family 146 slave lin interface controller (slic) motorola 14.4 external si gnal description the slic module has only two external signals which may be brought out to mcu pins. these might share fu nctionality with other mo dules or general-purpose input/output functions of the pins. when us ed in a lin system, these pins will be connected to the tx and rx pins of the lin physical layer. 14.4.1 slctx ? slic transmit pin the slctx pin serves as the serial output of the slic module. 14.4.2 slcrx ? slic receive pin the slcrx pin serves as the serial input of the slic module. this input feeds directly into the digital receive filter block which filters out noise glitches from the incoming data stream. 14.5 memory map/register definition table 14-1 shows the registers for the slic module. 14.6 slic register s and control bits this subsection provides information about all registers and control bits associated with the slic module. table 14-1. slic module memory map address use access $0040 slic control register 1 (slcc1) r/w $0041 slic control register 2 (slcc2) r/w $0042 slic status register (slcs) r/w $0043 slic prescaler register (slcp) r/w $0044 slic bit time register high (slcbth) r/w $0045 slic bit time register low (slcbtl) r/w $0046 slic state vector register (slcsv) r $0047 slic data length code register (slcdlc) r/w $0048 slic identifier register (slcid) r/w $0049 slic data register 7 (slcd7) r/w $004a slic data register 6 (slcd6) r/w $004b slic data register 5 (slcd5) r/w $004c slic data register 4 (slcd4) r/w $004d slic data register 3 (slcd3) r/w $004e slic data register 2 (slcd2) r/w $004f slic data register 1 (slcd1) r/w $0050 slic data register 0 (slcd0) r/w slave lin interface controller (slic) slic registers and control bits mc68hc908ql family data sheet motorola slave lin interface controller (slic) 147 14.6.1 slic control register 1 slic control register 1 (slcc1) contains bits used to control various basic features of the slic module, including features used for initialization and at runtime. initreq ?initialization request requesting initialization mode by setting th is bit will place th e slic module into its initialized state immediately. if transmission or reception of data is in progress, the transaction will be term inated immediately upon entry into initialization mode (signified by initack being set to 1). to return to normal slic operation after the slic has been initialized (the initack is high), the initreq has to be cleared by software. 1 = request for slic to be put into reset state immediately 0 = normal operation waketx ? transmit wakeup symbol this bit allows the user to transmit a wakeup symbol on the lin bus. when set, this sends a wakeup symbol, as defined in the lin specification a single time, then resets to 0. this bit will read 1 while the wakeup symbol is being transmitted on the bus. this bit will be automatically cleared when the wakeup symbol is complete. 1 = send wakeup symbol on lin bus 0 = normal operation txabrt ? transmit abort message 1 = transmitter aborts current transmi ssion at next byte boundary; txabrt resets to 0 after the transmission is successfully aborted 0 = normal operation imsg ? slic ignore message bit the imsg bit cannot be cleared by a writ e of 0, but is cleared automatically by the slic module after the next br eak/sync symbol pair is validated. 1 = slic to ignore data field of message, slic interrupts are suppressed until the next message header arrives 0 = normal operation slcie ? slic interrupt enable 1 = slic interrupt sources are enabled 0 = slic interrupt sources are disabled address: $0040 bit 7654321bit 0 read: 0 0 initreq 0 waketx txabrt imsg slcie write: reset:00100000 = unimplemented figure 14-4. slic control register 1 (slcc1) slave lin interface controller (slic) data sheet mc68hc908ql family 148 slave lin interface controller (slic) motorola 14.6.2 slic control register 2 slic control register 2 (slcc2) contains bits used to control various features of the slic module. slcwcm ? slic wait clock mode this bit can only be written once out of reset state. 1 = slic clocks stop when the cpu is placed into wait mode 0 = slic clocks continue to run when the cpu is placed into wait mode so that the slic can receive messages and wakeup the cpu. btm ? uart byte transfer mode byte transmit mode bypasses the norma l lin message framing and checksum monitoring and allows the user to s end and receive single bytes in a method similar to a half-duplex uart. when ena bled, this mode reads the bit time register (slcbt) value and assumes this is the value corresponding to the number of slic clock counts for one bit time to establish the desired uart bit rate. the user software must initialize th is register prior to sending or receiving data, based on the input clock selection, prescaler stage choice, and desired bit rate. btm forces the data length in slcdlc register to one byte (dlc = 0x00) and disables the checksum circuitry so that chkmod has no effect. refer to 14.18 byte transfer mode operation for more detailed information about how to use this mode. btm sets up the slic module to send and receive one byte at a time, with 8-bit data, no parity, and 1 stop bit (8-n-1). this is the most commonly used setup for uart communications and should work for most applications. this is fixed in the slic and is not configurable. 1 = uart byte transfer mode enabled 0 = uart byte transfer mode disabled slce ? slic module enable 1 = slic module enabled 0 = slic module disabled note: in order to guarantee timing, the user mu st ensure that clock source used allows the proper communications timing toleranc es and therefore internal oscillator circuits might not be appropriate for use with btm mode. address: $0041 bit 7654321bit 0 read:0000 slcwcm btm 0 slce write: reset:00000000 = unimplemented figure 14-5. slic control register 2 (slcc2) slave lin interface controller (slic) slic registers and control bits mc68hc908ql family data sheet motorola slave lin interface controller (slic) 149 14.6.3 slic status register slic status register (slcs) contains bits used to monitor the status of the slic module. slcact ? slic active (oscillat or trim blocking semaphore) slcact is used to indicate if it is safe to trim the oscillator based upon current slic activity. this bit indicates that the slic module might be currently receiving a message header, synchronizati on byte, id byte, or sending or receiving data bytes. this bit is read-only. 1 = slic module activity (not safe to trim oscillator) slcact is automatically set to 1 if a falling edge is seen on the slcrx pin and has successfully been passed th rough the digital rx filter. this edge is the potential beginning of a lin message frame. 0 = slic module not active (safe to trim oscillator) the slcact bit is cleared by the slic module only upon assertion of the rx message buffer full checksum ok (slcsv = $10) or the tx message buffer empty checksum transmitted (slcsv = $08) interrupt sources. initack ? initialization mode acknowledge initack indicates whether the slic module is in the reset mode as a result of writing initreq in slcc1. while in the reset state the slic module clocks are stopped. clearing the initreq allows the slic to proceed and enter slic run mode (if slce is set). the module will clear initack once the module has left reset mode and the slic will seek the ne xt lin header. this bit is read-only. 1 = slic module is in reset state 0 = normal operation slcf ? slic interrupt flag the slcf interrupt flag indicates if a slic module interrupt is pending. if set, the slcsv is then used to determine what interrupt is pending. this flag is cleared by writing a 1 to the bit. if additional interrupt sources are pending, the bit will be automatically set to 1 again by the slic. 1 = slic interrupt pending 0 = no slic interrupt pending address: $0042 bit 7654321bit 0 read:slcact0initack0000 slcf write: reset:00100000 = unimplemented figure 14-6. slic status register (slcs) slave lin interface controller (slic) data sheet mc68hc908ql family 150 slave lin interface controller (slic) motorola 14.6.4 slic prescaler register slic prescaler register (slcp) is used to divide the cpu bus clock for the digital receive filter circuit. the slic clock is divided through a prescaler (controlled by rxfp[1:0]) to drive the digital receive ci rcuit. variations on the input clock will propagate through these prescale stages, so if internal oscillators are used, worst case oscillator frequencies must be ac counted for when determining prescaler settings to ensure that the frequency of the slic clock always remains between 2 mhz and 8 mhz. rxfp[1:0] ? receive filter prescaler these bits set the prescale value for the cl ock for the digital receive filter circuit. this is a further prescaling of the slic input clock, which must be kept between 2 mhz and 8 mhz for proper slic operation in lin. the rxfp bits control the speed of the clock feeding the digital rece ive filter circuit, which determines the total maximum filter delay. any pulse which is smaller than the maximum filter delay value will be rejected by the filter and ignored as noise. for this reason, the user must choose the prescaler value appropriately to ensure that all valid message traffic is able to pass the filter fo r the desired bit rate. for more details about setting up the digital receive filter, please refer to 14.20 digital receive filter . address: $0043 bit 7654321bit 0 read: rxfp1 rxfp0 000000 write: reset:10000000 = unimplemented figure 14-7. slic prescale register (slcp) table 14-2. digital receive filter clock prescaler rxfp[1:0] digital rx filter clock prescaler (divide by) maximum filter delay (in s) slic clock (in mhz) 23.24 6 6.48 $00 1 8 5 4 2.67 2.5 2 $01 2 16 10 8 5.33 5 4 $10 3 (default) 24 15 12 8 7.5 6 $11 4 32 20 16 10.67 10 8 slave lin interface controller (slic) slic registers and control bits mc68hc908ql family data sheet motorola slave lin interface controller (slic) 151 the frequency of the slic clock must be between 2 mhz and 8 mhz, factoring in worst case possible numbers due to untr immed process variations, as well as temperature and voltage variations in os cillator frequency. this will guarantee greater than 1.5% accuracy for all lin messages from 1?20 kbps. the faster this input clock is, the greater the resulti ng accuracy and the higher the possible bit rates at which the slic can send and receive. in lin systems, the bit rates will not exceed 20 kbps; however, the slic modu le is capable of much higher speeds without any configuration changes, for cases such as high-speed downloads for reprogramming of flash memory or di agnostics in a test environment where radiated emissions requirements are not as stringent. in these situations, the user may choose to run faster than the 20 kbps limit which is imposed by the lin specification for emc reasons. details of how to calculate maximum bit rates and operate the slic above 20 kbps are detailed in 14.17 high-speed lin operation . refer to 14.9 slic module initialization procedure for more information on when to set up this register. 14.6.5 slic bit time registers note: in this subsection, the slic bit time regi sters are collectively referred to as slcbt. in lin operating mode (btm = 0), the slcbt is updated by the slic upon reception of a lin break-synch combin ation and provides the number of slic clock counts that equal one lin bit time to the user software. this value can be used by the software to calculate the clock drift in the oscillator as an offset to a known count value (based on nominal os cillator frequency and lin bus speed). the user software can then trim the oscillator to compensate for clock drift. refer to 14.19 oscillator trimming with slic for more information on this procedure. the user cannot read the bit time value from slcbth and slcbtl any time after the identifier byte is received until the beginning of the next lin message frame on the bus. the beginning of this message fr ame activity will be indicated by the slcact bit. when in byte transfer mode (btm = 1), the slcbt must be written by the user to set the length of one bit at the desired bit rate in slic clock counts. the user software must initialize this number prior to sending or receiving data, based on the input clock selection, prescaler stage choice, and desired bit rate. this setting is similar to choosing an input capture or output compare value for a timer. the closest even value should be chosen for this value, as bt0 will be forced to 0 by the slic module and any odd value will al ways be reduced to the next lowest even integer value. for example, a write of val ue 51 (0x33) will be forced to value of 50 and read back as 0x32. a write to both registers is required to update the bit time value. note: the slic bit time will not be updated until a write of the slcbtl has occurred. slave lin interface controller (slic) data sheet mc68hc908ql family 152 slave lin interface controller (slic) motorola bt ? bit time value bt displays the number of slic clocks that equals one bit time in lin mode (btm = 0). for details of the use of the slcbt registers in lin mode for trimming of the internal oscillator, refer to 14.19 oscillator trimming with slic . bt sets the number of slic clocks that equals one bit time in byte transfer mode (btm = 1). for details of the use of the slcbt registers in btm mode, refer to 14.18 byte transfer mode operation . 14.6.6 slic state vector register slic state vector register (slcsv) is provided to substantially decrease the cpu overhead associated with servicing interrupts while under operation of a lin protocol. it provides an index offset that is directly related to the lin module?s current state, which can be used with a us er supplied jump table to rapidly enter an interrupt service routine. this eliminates the need for the user to maintain a duplicate state machine in software. read: any time write: ignored i[3:0] ? interrupt state vector (bits 5?2) these bits indicate the source of the interrupt request that is currently pending. address: $0044 bit 7654321bit 0 read: 0 0 0 bt12 bt11 bt10 bt9 bt8 write: reset:00000000 = unimplemented figure 14-8. slic bit time register high (slcbth) address: $0045 bit 7654321bit 0 read: bt7 bt6 bt5 bt4 bt3 bt2 bt1 0 write: reset:00000000 = unimplemented figure 14-9. slic bit time register low (slcbtl) address: $0046 bit 7654321bit 0 read:0 0 i3i2i1i0 0 0 write: reset:00000000 = unimplemented figure 14-10. slic state vector register (slcsv) slave lin interface controller (slic) slic registers and control bits mc68hc908ql family data sheet motorola slave lin interface controller (slic) 153 14.6.6.1 lin mode operation table 14-3 shows the possible values for the possible sources for a slic interrupt while in lin mode operation (btm = 0). no interrupts pending this value indicates that all pending interrupt sources have been serviced. in polling mode, the slcsv is read a nd interrupts serviced until this value reads back 0. this source will not generate an interrupt of the cpu, regardless of state of the slcie bit. no bus activity (lin specified error) the no-bus-activity condition occurs if no valid synch break field or byte field was received for more than t timeout (as defined in lin protocol specification) since the reception of the last valid message. tx message buffer empty ? checksum transmitted when the entire lin message frame has been transmitted successfully, complete with the appropriately selected checksum byte, this interrupt source is asserted. this source is used for all standard lin message frames and the final set of bytes with extended lin message frames. table 14-3. interrupt sources summary (btm = 0) slcsv i3i2i1i0 interrupt source priority $00 0 0 0 0 no interrupts pending 0 (lowest) $04 0 0 0 1 no-bus-activity 1 $08 0010 tx message buffer empty checksum transmitted 2 $0c 0 0 1 1 tx message buffer empty 3 $10 0100 rx message buffer full checksum ok 4 $14 0101 rx data buffer full no errors 5 $18 0 1 1 0 bit-error 6 $1c 0 1 1 1 receiver buffer overrun 7 $20 1 0 0 0 (reserved) 8 $24 1001 checksum error 9 $28 1 0 1 0 byte framing error 10 $2c 1 0 1 1 identifier received successfully 11 $30 1 1 0 0 identifier parity error 12 $34 1 1 0 1 inconsistent-s ynch-field-error 13 $38 1 1 1 0 reserved 14 $3c 1 1 1 1 wakeup 15 (highest) slave lin interface controller (slic) data sheet mc68hc908ql family 154 slave lin interface controller (slic) motorola tx message buffer empty this interrupt source indicates that all 8 bytes in the lin message buffer have been transmitted with no checksum appended. this source is used for intermediate sets of 8 bytes in extended lin message frames. rx message buffer full ? checksum ok when the entire lin message frame has been received successfully, complete with the appropriately selected checksum byte, and the checksum calculates correctly, this interrupt source is asserted. this source is used for all standard lin message frames and the final set of bytes with extended lin message frames. in order to clear this source, the slcd0 register must be read. rx data buffer full ? no errors this interrupt source indicates that 8 bytes have been received with no checksum byte and are waiting in the lin message buffer. this source is used for intermediate sets of 8 byte s in extended lin message frames. in order to clear this source, the slcd0 register must be read. bit error a unit that is sending a bit on the bus also monitors the bus. a bit_error has to be detected at that bit time, when the bit value that is monitored is different from the bit value that is sent. the slic will terminate the data transmission at the next byte boundary, according to the lin specification. bit errors are not checked when the lin bus is running at high speed due to the effects of physical layer round trip delay. bit errors are fully checked at all lin 2.0 compliant speeds of 20 kbps and below. receiver buffer overrun error this error is an indication that the receive buffer has not been emptied and additional bytes have been received, resulting in lost data. reserved this source is reserved for future use. checksum error (lin specified error) the checksum error occurs when the calculated checksum value does not match the expected value. if this error is encountered, it is important to verify that the correct checksum calculation method was employed for this message frame. refer to the lin specification for more details on the calculations. byte framing error this error comes from the standard uart definition for byte encoding and occurs when the stop bit is sampled an d reads back as a 0. the stop bit should always read as 1. identifier received successfully this interrupt source indicates that a lin identifier byte has been received with correct parity and is waiting in the lin identifier buffer (slcid). upon slave lin interface controller (slic) slic registers and control bits mc68hc908ql family data sheet motorola slave lin interface controller (slic) 155 reading this interrupt source from t he slcsv register, the user can then decode the identifier in software to determine the nature of the lin message frame. in order to clear this source, the slcid register must be read. identifier-parity-error a parity error in the identifier (i.e., corrupted identifier) will be flagged. typical lin slave applications do not distinguish between an unknown but valid identifier, and a corrupted identifier. however, it is mandatory for all slave nodes to evaluate in case of a known identifier all 8 bits of the id-field and distinguish between a known and a corrupted identifier. the received identifier value is reported in the slcid register so that the user software can choose to acknowledge or ignore the parity error message. inconsistent-synch-field-error an inconsistent-synch-field-error has to be detected if a slave detects the edges of the synch field outside the given tolerance. reserved this source is reserved for future use. wakeup the wakeup interrupt source indicates that the slic module has entered slic run mode from slic wait or slic stop mode. 14.6.6.2 byte transfer mode operation when byte transfer mode is enabled (btm = 1), many of the interrupt sources for the slcsv no longer apply, as they are specific to lin operations. table 14-4 shows those interrupt sources which are applicable to btm operations. the value of the slcsv for each interrupt source remains the same, as well as the priority of the interrupt source. i table 14-4. interrupt sources summary (btm = 1) slcsv i3 i2 i1 i0 interrupt source priority $00 0000 no interrupts pending 0 (lowest) $0c 0011 tx message buffer empty 3 $14 0101 rx data buffer full no errors 5 $18 0110 bit-error 6 $1c 0111 receiver buffer overrun 7 $28 1010 byte framing error 10 $38 1110 reserved 14 $3c 1111 wakeup 15 (highest) slave lin interface controller (slic) data sheet mc68hc908ql family 156 slave lin interface controller (slic) motorola no interrupts pending this value indicates that all pending interrupt sources have been serviced. in polling mode, the slcsv is read a nd interrupts serviced until this value reads back 0. this source will not generate an interrupt of the cpu, regardless of state of the slcie bit. tx message buffer empty in byte transfer mode, this interrupt source indicates that the byte in the slcid has been transmitted. rx data buffer full ? no errors this interrupt source indicates that a byte has been received and is waiting in the slcid register. in order to clear this source, the slcid register must be read. bit-error a unit that is sending a bit on the bus also monitors the bus. a bit_error has to be detected at that bit time, when the bit value that is monitored is different from the bit value that is sent. receiver buffer overrun error the receiver buffer overrun error occurs when the number of bytes received by the slic module exceeds the value written to the slcdlc. if this error is encountered, ensure that the correct data length value is associated with the proper identifier in software. this error can also be an indication that the receive buffer has not been empt ied and additional byte(s) have been received, resulting in lost data. byte framing error this error comes from the standard uart definition for byte encoding and occurs when the stop bit is sampled an d reads back as a 0. the stop bit should always read as 1. reserved this source is reserved for future use. wakeup the wakeup interrupt source indicates that the slic module has entered slic run mode from slic wait or slic stop mode. 14.6.7 slic data length code register the slic data length code register (slcdlc) is the primary functional control register for the slic module during normal lin operations. it contains the data length code of the message buffer, indica ting how many bytes of data are to be sent or received, as well as the chec ksum mode control and transmit enabling bit. slave lin interface controller (slic) slic registers and control bits mc68hc908ql family data sheet motorola slave lin interface controller (slic) 157 txgo ? slic transmit go this bit controls whether the slic module is sending or receiving data bytes. this bit is automatically reset to 0 once a transmit operation is complete or an error is encountered and transmission has been aborted. 1 = initiate slic transmit the slic assumes the user has loaded the proper data into the message buffer and will begin transmitting the num ber of bytes indicated in the slcdlc bits. if the number of bytes is greater than 8, the first 8 bytes will be transmitted and an interrupt will be tr iggered (if unmasked) for the user to enter the next bytes of the message. if the number of bytes is 8 or fewer, the slic will transmit the appropriate number of bytes and automatically append the checksum to the transmission. 0 = slic receive data chkmod ? lin checksum mode chkmod is used to decide what checksum method to use for this message frame. resets after error code or message frame complete. 1 = checksum calculated without the identifier byte (lin spec <= 1.3) 0 = checksum calculated with the identifier byte included (sae j2602/lin 2.0) dlc ? data length control bits the value of the bits indicate the number of data bytes in message. values $00?$07 are for ?normal? lin messaging. values $08?$3f are for "extended" lin messaging. address: $0047 bit 7654321bit 0 read: txgo chkmod dlc5 dlc4 dlc3 dlc2 dlc1 dlc0 write: reset:00000000 figure 14-11. slic data length code register (slcdlc) table 14-5. data length control dlc[5:0] message data length (number of bytes) $00 1 $01 2 $02 3 ... ... $3d 62 $3e 63 $3f 64 slave lin interface controller (slic) data sheet mc68hc908ql family 158 slave lin interface controller (slic) motorola 14.6.8 slic identifier and data registers the slic identifier (slcid) and data regi sters (slcd[7:0]) comprise the transmit and receive buffer and are used to read/write the identifier and message buffer 8 data bytes. in btm mode (btm = 0), only the slcid register is used to send and receive bytes, as only one byte is handled at any one time. the number of bytes to be read from or written to these register s is determined by the user software and written to the slcdlc register. in order to obtain proper data, reads and writes to these registers must be made based on the proper length corresponding to a particular message. it is the responsibility of the user software to keep track of this value in order to prevent data corruption. for example, it is possible to read data from locations in the message buffer which c ontain erroneous or old data if the user software reads more data registers than were updated by the incoming message, as indicated in the slcdlc. note: an incorrect length value written to the slcdlc register can result in the user software misreading or miswriting data in the message buffer. an incorrect length value might also result in slic error messages. for example, if a 4-byte message is to be received, but the user software incorrectly reports a 3-byte length to the dlc, the slic will assume the 4th data byte is actually a checksum value and attempt to validate it as such. if this value doesn?t match the calculated value, an incorrect checksum error will occur. if it does happen to match the expected value, then the message would be received as a 3-byte message with valid checksum. either case is incorrect behavior for the application and can be avoided by ensuring that the correct length code is used for each identifier. the first data byte received after the lin identifier in a lin message frame will be loaded into slcd0. the next byte (if applicable) will be loaded into slcd1, and so forth. . the slic identifier register is used to capture the incoming lin identifier and when the slcsv value indicates that the identi fier has been received successfully, this register contains the received identifier value. if the incoming identifier contained a parity error, this register value will not contain valid data. in byte transfer mode (btm = 1), this register is used for sending and receiving each byte of data. address: $0048 bit 7654321bit 0 read:r7r6r5r4r3r2r1r0 write: t7 t6 t5 t4 t3 t2 t1 t0 reset:00000000 figure 14-12. slic identifier register (slcid) slave lin interface controller (slic) slic registers and control bits mc68hc908ql family data sheet motorola slave lin interface controller (slic) 159 address: $0049 bit 7654321bit 0 read:r7r6r5r4r3r2r1r0 write: t7 t6 t5 t4 t3 t2 t1 t0 reset:00000000 figure 14-13. slic data register 7 (slcd7) address: $004a bit 7654321bit 0 read:r7r6r5r4r3r2r1r0 write: t7 t6 t5 t4 t3 t2 t1 t0 reset:00000000 figure 14-14. slic data register 6 (slcd6) address: $004b bit 7654321bit 0 read:r7r6r5r4r3r2r1r0 write: t7 t6 t5 t4 t3 t2 t1 t0 reset:00000000 figure 14-15. slic data register 5 (slcd5) address: $004c bit 7654321bit 0 read:r7r6r5r4r3r2r1r0 write: t7 t6 t5 t4 t3 t2 t1 t0 reset:00000000 figure 14-16. slic data register 4 (slcd4) address: $004d bit 7654321bit 0 read:r7r6r5r4r3r2r1r0 write: t7 t6 t5 t4 t3 t2 t1 t0 reset:00000000 figure 14-17. slic data register 3 (slcd3) address: $004e bit 7654321bit 0 read:r7r6r5r4r3r2r1r0 write: t7 t6 t5 t4 t3 t2 t1 t0 reset:00000000 figure 14-18. slic data register 2 (slcd2) slave lin interface controller (slic) data sheet mc68hc908ql family 160 slave lin interface controller (slic) motorola r ? read slc receive data t ? write slc transmit data 14.7 initialization/a pplication information the lin specification defines a standard lin "message frame" as the basic format for transferring data across a lin network. a standard message frame is composed as shown in figure 14-21 (shown with 8 data bytes). lin transmits all data, identifier, and c hecksum characters as standard uart characters with 8 data bits, no parity, and 1 stop bit. therefore, each byte has a length of 10 bits, including the start and st op bits. the data bits are transmitted least significant bit (lsb) first. figure 14-21. typical lin message frame address: $004f bit 7654321bit 0 read:r7r6r5r4r3r2r1r0 write: t7 t6 t5 t4 t3 t2 t1 t0 reset:00000000 figure 14-19. slic data register 1 (slcd1) address: $0050 bit 7654321bit 0 read:r7r6r5r4r3r2r1r0 write: t7 t6 t5 t4 t3 t2 t1 t0 reset:00000000 figure 14-20. slic data register 0 (slcd0) synch break synch byte ident field data field data field data field data field data field data field data field checksum field data field 01 2345 67 0x55 13 or more bits (lin 1.3) header data slave lin interface controller (slic) initialization/applic ation information mc68hc908ql family data sheet motorola slave lin interface controller (slic) 161 14.7.1 lin message frame header the header section of all lin messages is transmitted by the master node in the network and contains synchronization data, as well as the identifier to define what information is to be contained in the message frame. formally, the header is comprised of three parts: 1. synch break 2. synch byte (0x55) 3. identifier field the first two components are present to allow the lin slave nodes to recognize the beginning of the message frame and derive the bit rate of the master module. the synch break allows the slave to s ee the beginning of a message frame on the bus. the slic module can receive a standard 10-bit break character for the synch break, or any break between 10?20 bit times in length. this encompasses the lin requirement of 13 or more bits of length for the synch break character. the synch byte is always a 0x55 data byte , providing five falling edges for the slave to derive the bit rate of the master node. the identifier byte indicates to the slave what is the nature of the data in the message frame. this data might be supplied from either the master node or the slave node, as determined at system design time. the slave node must read this identifier, check for parity errors, and deter mine whether it is to send or receive data in the data field. more information on the header is contained in 14.10.1 lin message headers . 14.7.2 lin data field the data field is comprised of standard byte s (8 data bits, no parity, 1 stop bit) of data, from 0?8 bytes for normal lin frames and greater than 8 bytes for extended lin frames. the slic module will either tr ansmit or receive these bytes, depending upon the user code interpretation of the identifier byte. data is always transmitted into the data field least si gnificant byte (lsb) first. the slic module can automatically handle up to 64 bytes in extended lin message frames without significant ly changing program execution. 14.7.3 lin checksum field the checksum field is a data integrity measure for lin message frames, used to signal errors in data consistency. the li n 1.3 checksum calculation only covers the data field, but the slic module also supports an enhanced checksum calculation which also includes the ident ifier field. for more information on the checksum calculation, refer to 14.16 lin data integrity checking methods . slave lin interface controller (slic) data sheet mc68hc908ql family 162 slave lin interface controller (slic) motorola 14.7.4 slic module constraints in designing a practical module, certain reasonable constraints must be placed on the lin message traffic which are not necessarily explicitly specified in the lin specification. the slic module presumes that: timeout for no-bus-activity = 1 second. 14.8 slcsv inte rrupt handling each change of state of the slic module is encoded in the slic state vector register (slcsv). this is an efficient method of handling state changes, indicating to the user not only the current status of the slic module, but each state change will also generate an interrupt (if slic interrupts are enabled). for more detailed information on the slcsv, please refer to 14.6.6 slic state vector register . in the software diagrams in the following subsections, when an interrupt is shown, the first step must always be reading the slcsv register to determine what is the current status of the slic module. likewise, when the diagrams indicate to "exit isr", the final step to exiting the interr upt service routine is to clear the slcf interrupt flag. this can only be done if the slcsv has first been read, and in the case that data has been received (such as an id byte or command message data) the slcd has been read at least one time. once the slcsv register is read, it will switch to the next pending state, so the user must be sure it is copied only once into a software variable at the beginning of the interrupt service routine in order to avoi d inadvertently clearing a pending interrupt source. additional decisions based on this va lue should be made from the software variable, rather than from the slcsv itself. after exiting the isr, normal application code may resume. if the diagram indicates to "return to idle," it indicates that all processing for the current message frame has been completed. if an error was detected and the corresponding error code loaded into the slcsv, any pending data in the data buffer will be flushed out and the slic returned to its idle state, seeking out the next message frame header. 14.9 slic module in itialization procedure 14.9.1 lin mode initialization the slic module does not require very much initialization, due to it?s self-synchronizing design. since no prior k nowledge of the bit rate is required in order to synchronize to the lin bus, no programming of bit rate is required. at initialization time, the user must configure: slic prescale register (slic digital receive filter adjustment). wait clock mode operation. slave lin interface controller (slic) slic module initia lization procedure mc68hc908ql family data sheet motorola slave lin interface controller (slic) 163 the slic clock is the same as the cpu bus clock. the module is designed to provide better than 1% bit rate accuracy at the lowest value of the slic clock frequency and the accuracy improves as the slic clock frequency is increased. for this reason, it is advantageous to choo se the fastest slic clock which is still within the acceptable operating range of the slic. since the slic may be used with mcus with internal oscillators, the tolerance of the oscillator must be taken into account to ensure that the slic clock frequency does not exceed the bounds of the slic clock operating range. this is es pecially important if the user wishes to use the oscillator untrimmed, where pr ocess variations might result in mcu frequency offsets of 25%. the acceptable range of slic clock frequencies is 2?8 mhz to guarantee lin operations with greater than 1.5% accuracy across the 1?20 kbps range of lin bit rates. the user must ensure that the fastest possible slic clock frequency never exceeds 8 mhz or that the slowest possi ble slic clock never falls below 2 mhz under worst case conditions. this would include, for example, oscillator frequency variations due to untrimmed oscillator tole rance, temperature variation, or supply voltage variation. in order to initialize the slic module into lin operating mode, the user should perform the following steps prior to needing to receive any lin message traffic. these steps assume the mcu has been reset either by a power-on reset (por) or any other mcu reset mechanism. the steps for slic initialization for lin operation are: 1. write slcc1 to clear initreq. 2. when initack = 0, write slcc1 & slcc2 with desired values for: a. slcwcm ? wait clock mode (default = leaving slic clock running when in cpu wait). 3. write slcp to set up prescalers for: a. rxfp ? digital receive filter clock prescaler (default = slic divided by 3). 4. enable the slic module by writing slcc2: a. slce = 1 to place slic module into run mode. b. btm = 0 to disable byte transfer mode (default). 5. write slcc1 to enable slic interrupts (if desired). 14.9.2 byte transfer mode initialization bit rate synchronization is handled aut omatically in lin mode, using the synchronization data contained in each li n message to derive the desired bit rate. in byte transfer mode (btm = 1); however, the user must set up the bit rate for communications using the clock selectio n, prescaler, and slcbt register. slave lin interface controller (slic) data sheet mc68hc908ql family 164 slave lin interface controller (slic) motorola more information on byte transfer mode is described in 14.18 byte transfer mode operation , including the performance param eters on recommended maximum speeds, bit time resolution, and os cillator tolerance requirements. once the desired settings of prescalers and bit time are determined, the slic initialization for btm operation is virtually identical to that of lin operation. the steps are: 1. write slcc1 to clear initreq. 2. when initack = 0, write slcc2 with desired values for: a. slcwcm ? wait clock mode (default = leaving slic clock running when in cpu wait). 3. write slcicp to set up prescalers for: a. rxfp ? digital receive filter clock prescaler (default = slic divided by 3). 4. enable the slic module by writing slcc2: a. slce = 1 to place slic module into run mode. b. btm = 1 to enable byte trans fer mode (default = disabled). 5. write slcc1 to enable slic interrupts (if desired). 14.10 handling li n message headers figure 14-22 shows how the slic module deals with incoming lin message headers. 14.10.1 lin message headers all lin message frame headers are comprised of three components: the first is the synchronization break (synch break) symbol, which is a dominant (low) pulse at leas t 13 or more bit times long, followed by a recessive (high) sync hronization delimiter of at least one bit time. in lin 2.0, this is allowed to be 10 or more bit times in length. the second part is called the synchronization field (synch field) and is a single byte with value 0x55. th is value was chosen as it is the only one which provides a series of five fall ing (recessive to dominant) transitions on the bus. the third section of the message frame header is the identifier field (id). the identifier is covered more in 14.11 handling command message frames and 14.12 handling request lin message frames . slave lin interface controller (slic) handling lin message headers mc68hc908ql family data sheet motorola slave lin interface controller (slic) 165 figure 14-22. handling lin message headers the slic automatically reads the in coming pattern of the synchronization break and field and determines the bit rate of the lin data frame, as well as checking for errors in form and disc erning between a genuine break/field combination and a similar byte pattern so mewhere in the data stream. once the header has been verified to be valid and has been processed, the slic module updates the slic bit time register (slicbt) with the value obtained from the synch field and begins to receive the id. process error code: lin message header received slic updates slcbt id arriving in rx buffer n y error code ? y n id for this ? n y node interrupt process valid id inconsistent-synch-field-error process error code: identifier-parity error set imsg bit framing error exit isr return to read id from slcid read slcsv lin bus idle valid break and synch data? interrupt read slcsv slave lin interface controller (slic) data sheet mc68hc908ql family 166 slave lin interface controller (slic) motorola if there are errors in the synch break/field pattern, then an interrupt is generated. if unmasked, it will trigger an mcu interrupt request and the resulting code in the slic state vector register (slcsv) will be an "inconsistent-synch-field-error," based on the lin protocol specification. once the id for the message frame has been received, an interrupt is generated by the slic and will trigger an mcu interrupt request if unmasked. at this point, it might be possible that the id was received with errors such as a parity error (based on the lin specification) or a byte frami ng error. if the id did not have any errors, it will be copied into the slcd for the software to read. the slcsv will indicate the type error or that the id was received correctly. in a lin system, the meaning and function of all messages, and therefore all message identifiers, is pre-defined by the sy stem designer. this information can be collected and stored in a standardized format file, called a configuration language description (cld) file. in using the slic module, it is the responsibility of the user software to determine the nature of the incoming message, and therefore how to further handle that message. the simplest case is when the slic receives a message which the user software determines is of no interest to the application. in other words, the slave node does not need to receive or transmit any data fo r this message frame. this might also apply to messages with zero data bytes (whi ch is allowed by the lin specification). at this point, the user can set the imsg control bit, and exit the interrupt service routine by clearing the slcif flag. because there is no data to be sent or received, the slic will not generate another interrupt until the next message frame header or bus goes idle long enough to trigger a "no-bus-activity" error according to the lin specification. note: imsg will prevent another interrupt from occurring for the current message frame; however, if data bytes are appearing on the bus they may be received and copied into the message buffer. this will delet e any previous data which might have been present in the buffer, even though no interrupt is triggered to indicate the arrival of this data. at the time the id is read, the user might also choose to read the slcbt register and copy this value out to an application variable. this data can then be used at a time appropriate to both the application software and the lin communications to adjust the trim of the internal oscillator. this operation must be handled very carefully to avoid adjusting the base timing of the mcu at the wrong time, adversely affecting the operation of the slic modul e or of the application itself. more information about this is contained in 14.19 oscillator trimming with slic . if the user software determines that the id read out of the slcd corresponds to a command or request message for which this node needs to receive or transmit data (respectively), it will then move on to procedures described in 14.11 handling command message frames and 14.12 handling request lin message frames . slave lin interface controller (slic) handling command message frames mc68hc908ql family data sheet motorola slave lin interface controller (slic) 167 for clarification, in this document, "c ommand" messages will refer to any message frame where the slic module is receiv ing data bytes and "request" messages refer to message frames where the slic module will be expected to transmit data bytes. this is a generic description and should not be confused with the terminology in the lin specification. the lin use of the terms "command" and "request" have the same basic meaning, but are limited in scope to specific identifier values of 0x3c and 0x3d. in the slic module documentation, these terms have been used to describe these f unctional types of messages, regardless of the specific identifier value used. 14.10.2 possible errors on message headers possible errors on message headers are: inconsistent-synch-field-error identifier-parity-error framing error 14.11 handling co mmand message frames figure 14-23 shows how to handle command message frames, where the slic module is receiving data from the master node. command message frames refer to lin messages frames where the master node is ?commanding? the slave node to do someth ing. the implication is that the slave will then be receiving data from the master for this message frame. this can be a standard lin message frame of 1?8 data bytes, a reserved lin system message (using 0x3c identifier), or an ext ended command message frame utilizing the reserved 0x3e user defined identifier or perhaps the 0x3f lin reserved extended identifier. the slic module is capable of handling message frames containing up to 64 bytes of data, while still automa tically calculating and/or verifying the checksum. 14.11.1 standard command message frames once the application software has read the incoming identifier and determined that it is a valid identifier which cannot be ig nored using the imsg bit, it must determine if this message frame is a command mess age frame or a request message frame. (i.e., should the application receive data fr om the master or send data back to the master?) the first case, shown in figure 14-23 deals with command messages, where the slic will be receiving data from the master node. if the received identifier corresponds to a standard lin command frame (i.e., 1?8 data bytes), the user must then write the number of bytes (determined by the system designer and directly linked with this particular identifier) corresponding to the length of the message frame into the slcdlc register. the two most significant bits of this register are used for special control bits describing the nature of this message frame. slave lin interface controller (slic) data sheet mc68hc908ql family 168 slave lin interface controller (slic) motorola figure 14-23. handling command messages (data receive) command message ? process valid id n y initialize sw byte count process request message extended frame ? y n write slcdlc for this id 0nxx xxxx (txgo = 0) (chkmod = n) exit isr error code ? y n process error code: exit isr return to idle 1. empty rx buffer 2. decrement sw byte count by 8 last frame ? y n (sw byte count 8) write slcdlc for this id 0n00 0xxx (txgo = 0) (chkmod = n) exit isr error code ? y n process error code: exit isr return to idle empty rx buffer framing error checksum-error no-bus-activity framing error no-bus-activity interrupt read slcsv interrupt read slcsv receive buffer overrun receive buffer overrun slave lin interface controller (slic) handling command message frames mc68hc908ql family data sheet motorola slave lin interface controller (slic) 169 the slic transmit go (txgo) bit should be 0 for command frames, indicating to the slic that data is coming from the master. the checksum mode control (chkmod) bit allows the user to select which method of checksum calculation is desired for this message frame. the lin 1.3 checksum does not include the identifier byte in the calculation, while the sae version does incl ude this byte. since the identifier is already received by the sl ic by this time, the default is to include it in the calculation. if a lin 1.3 checksum is desired, a 1 in the chkmod bit will reset the checksum circuitry to begin ca lculating the checksum on the first data byte. using the chkmod bit in this way al lows the slic to receive messages with either method of data consistency check and change on a frame-by-frame basis. if a system uses both types of data consistency checking methods, the software must simply change the setting of this bi t based on the identifier of each message. if the network only uses one type of che ck, the chkmod bit can be set as a constant value in the user?s code. if chkmod is not written on each frame, care must be taken not to accidentally modi fy the bit when writing the data length and txgo bits. this is especially true if us ing c code without carefully inspecting the output of the compiler and assembler. the control bits and data length code are contained in one register, allowing the user to maximize the efficiency of the i dentifier processing by writing a single byte value to indicate the nature of the message frame. this allows very efficient identifier processing code, which is important in a command frame, as the master node can be sending data immediately following the identifier byte which might be as little as one byte in length. the slic module uses a separate internal storage area for the incoming data bytes, so there is no danger of losing incoming data, but the user should spend as little time as possible within the isr to ensure that the application or other isrs are able to use the majority of the cpu bandwidth. the identifier must be processed in a ma ximum of 2 byte times on the lin bus to ensure that the isr completes before the checksum would be received for the shortest possible message. this should be easily achievabl e, as the only operations required are to read the slcid register and look up the checksum method, data length, and command/request state of that identifier, then write that value to the slcdlc. this can be easily streamlined in code with a lookup table of identifiers and corresponding slcdlc bytes. 14.11.2 extended command message frames handling of extended frames is very similar to handling of standard frames, providing that the length is less than or equal to 64 bytes. since the slic module can only receive 8 bytes at a time, the receive buffer must be emptied periodically for long message frames. this is not standard lin operation, and is likely only to be used for downloading calibration data or reprogramming flash devices in a factory or service facility, so the added steps required for processing are not as critical to performance. during these types of operations, the application code is likely very limited in scope and spec ial adjustments can be made to compensate for added message processing time. slave lin interface controller (slic) data sheet mc68hc908ql family 170 slave lin interface controller (slic) motorola for extended command frames, the data length is still written one time at the time the identifier is decoded, along with th e txgo and chkmod bits. when this is done, a software counter must also be initia lized to keep track of how many bytes are expected to be received in the message frame. the isr completes, clearing the slcf flag, and resumes application execution. the slic will generate an interrupt, if unmasked, after 8 bytes are received or an error is detected. at this interrupt, the slcsv will indicate an error condition (in case of framing error, idle bus) or that the receive buffer is full. if the data is successfull y received, the user must then empty the buffer by reading slcd7-slcd0 and then subtract 8 from the software byte count. when this software count er reaches 8 or fewer, the remaining data bytes will fit in the buffer and only one interrupt should occur. at this time, the final interrupt may be handled normally, continuing to use the software counter to read the proper number of bytes from the appropriate slcd registers. note: do not write the slcdlc register more than one time per lin message frame . the slic tracks the number of sent or received bytes based on the value written to this register at the beginning of the data field and rewriting this register will corrupt the checksum calculation and cause unpredictable behavior in the slic module . the application software must track the number of sent or received bytes to know what the current byte count in the slic is . if programming in c, make sure to use the volatile modifier on this variable (or make it a global variable) in order to ensure that it keeps it?s value between interrupts . 14.11.3 possible errors on command message data possible errors on command message data are: framing error checksum-error (lin specified error) no-bus-activity (lin specified error) receiver buffer overrun error 14.12 handling request lin message frames figure 14-24 shows how to handle request message frames, where the slic module is sending data to the master node. request message frames refer to lin me ssages frames where the master node is ?requesting? the slave node to supply informat ion. the implication is that the slave will then be transmitting data to the ma ster for this message frame. this can be a standard lin message frame of 1?8 data bytes, a reserved lin system message (using 0x3d identifier), or an extended request message frame utilizing the reserved 0x3e identifier or perhaps the 0x3f lin reserved extended identifier. the slic module is capable of handling reque st message frames containing up to 64 bytes of data, while still automatically ca lculating and/or verifying the checksum. slave lin interface controller (slic) handling request lin message frames mc68hc908ql family data sheet motorola slave lin interface controller (slic) 171 figure 14-24. handling request lin message frames process request message extended frame ? y n 3. write slcdlc for this id 1nxx xxxx (txgo = 1) (chkmod = n) exit isr error code ? y n process error code: exit isr return to idle decrement sw byte count by 8 last frame ? y n (sw byte count 8) 2. write slcdlc for this id 1n00 0xxx (txgo = 1) (chkmod = n) exit isr error code ? y n process error code: exit isr return to idle transmit complete 1. initialize sw byte count 2. load first 8 data bytes 1. load data into message buffer 1. load last ( 8) bytes to transmit framing error bit-error checksum-error framing error bit-error interrupt read slcsv interrupt read slcsv 2. write txgo bit to start transmit (1) 1. load next 8 bytes to transmit 2. write txgo bit to start transmit (1) note 1. when writing txgo bit only, ensure that chkmod and data length values are not accidentally modified. slave lin interface controller (slic) data sheet mc68hc908ql family 172 slave lin interface controller (slic) motorola 14.12.1 standard request message frames dealing with request messages with the slic is very similar to dealing with command messages, with one important differ ence. since the slic is now to be transmitting data in the lin message frame, the user software must load the data to be transmitted into the message buffer prior to initiating the transmission. this means an extra step is taken inside the inte rrupt service routine once the identifier has been decoded and is determined to be an id for a request message frame. figure 14-24 deals with request messages, where the slic will be transmitting data to the master node. if the received identifier corresponds to a standard lin command frame (i.e., 1-8 data bytes), the message processing is very simple. the user must load the data to be transmitted into the transmit buffer by writing it to the slcd registers. the first byte to be transmitted on the lin bus should be loaded into slcd0, then slcd1 for the second byte, etc. once all of the bytes to be transmitted are loaded in this way, a single write to the slcdlc register will allow the user to encode the number of data bytes to be transmitted (1?8 bytes for standard request frames), set the proper checksum calculation method for the data (chkmod), as well as signal the slic that the buffer is ready by writing a 1 to the txgo bit. the txgo bit will remain set to 1 until the buffer is sent successfully or an error is encountered, signaling to the application code that the buffer is in process of transmitting. in cases of 1?8 data bytes only being sent (standard lin request frames), the slic automatically calculates and transmits the checksum byte at the end of the message frame. th e user can exit the isr once the slcdlc register has been written and the slcf flag has been cleared. the next slic interrupt which occurs, if unmasked, will indicate the end of the request message frame and will either indicate that the frame was properly transmitted or that an error was encountered during transmission. refer to 14.12.4 possible errors on request message data for more detailed explanation of these possible errors. this interrupt also signals to the application that the message frame is complete and all data bytes and the checksum value have been properly transmitted onto the bus. the slic module cannot begin to transmit the data until the user writes a 1 to the txgo bit, indicating that data is ready. if the user writes the txgo bit without loading data into the transmit buffer, whatever data is in storage will be transmitted, where the number of bytes transmitted is based on the data length value in the data length register. similarly, if the user wr ites the wrong value for the number of data bytes to transmit, the slic will transmit that number of bytes, potentially transmitting garbage data onto the bus. the checksum calculation is performed based on the data transmitted, and will therefore still be calculated. the identifier must be processed, data must be loaded into the transmit buffer, and the slcdlc value written to initiate data transmission in a certain amount of time, based on the lin specification. if the user waits too long to start transmission, the master node will observe an idle bus and trigger a slave not responding error condition. the same error can be trigger ed if the transmission begins too late and slave lin interface controller (slic) handling request lin message frames mc68hc908ql family data sheet motorola slave lin interface controller (slic) 173 does not complete before the message frame times out. refer to the lin specification for more details on timing constraints and requirements for lin slave devices. this is especially important when dealing with extended request frames, when the data must be loaded in 8 byte sections (maximum) to be transmitted at each interrupt. 14.12.2 extended request message frames handling of extended frames is very similar to handling of standard frames, providing that the length is less than or equal to 64 bytes. since the slic module can only transmit 8 bytes at a time, the transmit buffer must be loaded periodically for extended message frames. this is not standard lin operation, and is likely only to be used for special cases, so the added steps required for processing should not be as critical to performance. during th ese types of operations, the application code is likely very limited in scop e and special adjustments can be made to compensate for added message processing time. for extended request frames, the data length is still written on ly one time, at the time the identifier is decoded, along with the txgo and chkmod bits, after the first 8 data bytes are loaded into the transmit buffer. when this is done, a software counter must also be initialized to keep track of how many bytes are to be transmitted in the message frame. the isr completes, clearing the slcf flag, and resumes application execution. the slic will generate an interrupt, if unmasked, after 8 bytes are transmitted or an error is detected. at this interrupt, the slcsv will indicate an error condition (in case of framing error or bit error) or that the transmit buffer is empty. if the data is transmitted successfully, the user must then subtract 8 from the software byte coun t, load the next 8 bytes into the slcd registers, and write a 1 to the txgo bit to tell the slic that the buffers are loaded and transmission can commence. when this software counter reaches 8 or fewer, the remaining data bytes will fit in the transmit buffer and the slic will automatically append the checksum value to the frame after the last byte is sent. note: do not write the chkmod or data length values in the slcdlc register more than one time per message frame . the slic tracks the number of sent or received bytes based on the value written to this register at the beginning of the data field and rewriting this register will corrupt the checksum calculation and cause unpredictable behavior in the slic module . the application software must track the number of sent or received bytes to know what the current byte count in the slic is . if programming in c, make sure to use the volatile modifier on this variable (or make it a global variable) in order to ensure that it keeps it?s value between interrupts . 14.12.3 transmit abort the transmit abort bit (txabrt) in slcc1 allows the user to cease transmission of data on the next byte boundary. when this bit is set to 1, it will finish transmitting the byte currently being transmitted, then cease transmission. once the transmission is succ essfully aborted, the txabrt bi t will automatically be reset by slave lin interface controller (slic) data sheet mc68hc908ql family 174 slave lin interface controller (slic) motorola the slic to 0. if the slic is not in proc ess of transmitting at the time txabrt is written to 1, there is no effect and txabrt will read back as 0. 14.12.4 possible errors on request message data possible errors on request message data are: framing error. checksum-error (lin specified error). bit-error. 14.13 handling imsg to minimize interrupts the imsg feature is designed to minimize the number of interrupts required to maintain lin communications. on a network wi th many slave nodes, it is very likely that a particular slave will observe mess ages which are not intended for that node. when the slic module detects any message header, it synchronizes to that message frame and bit rate, then interrupts the cpu once the identifier byte has been successfully received and parity chec ked. at this time, if the software determines that the message may be ignored, the imsg bit may be set to indicate to the module that the data field of the message frame is to be ignored and no additional interrupts should be generated until the next valid message header is received. the bit is automatically reset to 0 once the current message frame is complete and the lin bus returns to idle state. this reduces the load on the cpu and allows the application software to immediately begin performing any operations which might otherwise not be allowed while receiving messaging. note: imsg will prevent another interrupt from occurring for the current message frame, however if data bytes are appearing on the bus they may be received and copied into the message buffer. this will delet e any previous data which might have been present in the buffer, even though no interrupt is triggered to indicate the arrival of this data. 14.14 sleep and wakeup operation the slic module itself has no specia l sleep mode, but does support low-power modes and wake-up on network activity. for low-power operations, the user must select whether or not to allow the slic clock to continue operating when the mcu issues a wait instruction through the slc wait clock mode (slcwcm) bit in slcc1 register. if slcwcm = 1, the slic will enter slic stop mode when the mcu executes a wait instruction. if slcwcm = 0, the slic will enter slic wait mode when the mcu executes a wait instruction. for more information on these modes, as well as wakeup options from these modes, please refer to 14.3 modes of operation . when network activity occurs, the slic module will wake the mcu out of stop or wait mode, and return the slic module to slic run mode. the slcsv register will slave lin interface controller (slic) polling operation mc68hc908ql family data sheet motorola slave lin interface controller (slic) 175 indicate wakeup as the interrupt source so that the user knows that the slic module brought the mcu out of stop or wait. in a lin system, a system message is generally sent to all nodes to indicate that they are to enter low-power network sleep mode. once a node enters sleep mode, it waits for outside events, such as switch or sensor inputs or network traffic to bring it out of network sleep mode. if the node using the slic module is awakened by a source other than network traffic, such as a switch input, the lin specification requires this node to issue a wake-up signal to the rest of the network. the slic module supports this feat ure using the waketx bit in the slcc2 register. the user software may set this bit and one lin wake-up signal is immediately transmitted on the bus, then the bit is autom atically cleared by the slic module. if another wake-up signal is required to be sent, the user must set the waketx bit again. in a lin system, the lin physical interfac e can often also provide an output to the irq pin to provide a wake-up mechanism on network activity. the physical layer might also control voltage regulation suppl y to the mcu, cutting power to the mcu when the physical layer is placed in its low-power mode. the user must take care to ensure that the interaction between the physical layer, irq pin, slic transmit and receive pins, and power supply regula tor is fully understood and designed to ensure proper operation. 14.15 polling operation it is possible to operate the slic module in polling mode, if desired. the primary difference is that the slic interrupt request should not be enabled (slcie = 0). the slcsv will update and operate properly and interrupt requests will be indicated with the slcf flag, which can be polled to determine status changes in the slic module. it is required that the polling rate be fast enough to ensure that slic status changes be recognized and pr ocessed in time to ensure that all application timings can be met. 14.16 lin data int egrity checking methods the slic module supports two different lin-based data integrity options: the first option supports lin 1. 3 and older methods of checksum calculations. the second option supports an opt ional additional enhanced checksum calculation which has greater data integrity coverage. the lin 1.3 and earlier specifications transmit a checksum byte in the "checksum field" of the lin message frame. this checksum field contains the inverted modulo-256 sum over all data bytes. the sum is calculated by an "add with carry" where the carry bit of each addition is added to the least significant bit (lsb) of it?s resulting sum. this guarantees security also for the slave lin interface controller (slic) data sheet mc68hc908ql family 176 slave lin interface controller (slic) motorola msbs of the data bytes. the sum of modulo-256 sum over all data bytes and the checksum byte must be?0xff?. an optional checksum calculation can al so be performed on a lin data frame which is very similar to the lin 1.3 calcul ation, but with one important distinction. this enhanced calculation simply includes the identifier field as the first value in the calculation, whereas the lin 1.3 calculation begins with the least significant byte of the data field (which is the first byte to be transmitted on the bus). this enhanced calculation further ensures that the identif ier field is correct and ties the identifier and data together under a common calculation, ensuring greater reliability. in the slic module, either checksum calculation can be performed on any given message frame by simply writing or clearing the chkmod bit in the slcdlc register, as desired, when the identifier for the message frame is decoded. the appropriate calculation for each message frame should be decided at system design time and documented in the lin descri ption file, indicating to the user which calculation to use for a particular identifier. 14.17 high-speed lin operation high-speed lin operation does not necessar ily require any rec onfiguration of the slic module, depending upon what maximum lin bit rate is desired. several factors affect the performance of the slic module at lin speeds higher than 20 kbps, all of which are functions of t he speed of the slic clock and the prescaler of the digital filter. the tightest constraint comes from the need to maintain 1.5% accuracy with the master node timing. this requires that the slic module be able to sample the incoming data stream accurately enough to guarantee that accuracy. table 14-6 shows the maximum lin bit rates allowable in order to maintain this accuracy. table 14-6. maximum lin bit rates for high-speed operation slic clock (mhz) maximum lin bit rate for 1% slic accuracy (bits / second) maximum lin bit rate for 1.5% slic accuracy (bits / second) 8 80,000 120,000 6.4 64,000 96,000 4.8 48,000 72,000 4 40,000 60,000 3.2 32,000 48,000 2.4 24,000 36,000 2 20,000 30,000 slave lin interface controller (slic) high-speed lin operation mc68hc908ql family data sheet motorola slave lin interface controller (slic) 177 the above numbers assume a perfect input waveforms into the slcrx pin, where 1 and 0 bits are of equal length and are exactly the correct length for the appropriate speed. factors such as physical layer wave shaping and ground shift can affect the symmetry of these wavefo rms, causing bits to appear shortened or lengthened as seen by the slic module. the user must take these factors into account and base the maximum speed upon the shortest possible bit time that the slic module may observe, factoring in all physical layer effects. on some lin physical layer devices it is possible to turn off wave shaping circuitry for high-speed operation, removing this portion of the physical layer error. the digital receive filter can also affect high speed operation if it is set too low and begins to filter out valid message traffi c. under ideal conditions, this will not happen, as the digital filter maximum s peeds allowable are higher than the speeds allowed for 1.5% accuracy. if the digital re ceive filter prescaler is set to divide- by-4; however, the filter delay is very close to the 1.5% ac curacy maximum bit time. for example, with a slic clock of 4 mhz, the slic module is capable of maintaining 1.5% accuracy up to 60,000 bps. if the digital receive filter prescaler is set to divide-by-4, this means that th e filter will only pass message traffic which is 62,500 bps or slower under ideal circum stances. this is only a difference of 2,500 bps (4.17% of the nominal valid mess age traffic speed). in this case, the user must ensure that with all errors accounted for, no bit will appear shorter than 16 s (1 bit at 62,500 bps) or the filter will bloc k that bit. this is fa r too narrow a margin for safe design practices. the better solution would be to reduce the filter prescaler, increasing the gap between the filter cut-off point and the nominal speed of valid message traffic. changing the prescaler to divide by 2 in this example gives a filter cut-off of 125,000 bps, which is 60,000 bps faster than the nominal speed of the lin bus and much less likely to interfere with valid message traffic. to ensure that all valid messages pass the filter stage in high-speed operation, it is best to ensure that the filter cut-off point is at least 2 times the nominal speed of the fastest message traffic to appear on the bus. refer to table 14-6 for a more complete list of the digital receive filter delays as they relate to the maximum lin bus frequency. table 14-7 repeats much of the data found in table 14-6 ; however, the filter delay values have been converted to the frequency domain. slave lin interface controller (slic) data sheet mc68hc908ql family 178 slave lin interface controller (slic) motorola 14.18 byte transfer mode operation this subsection describes t he operation and limitations of the optional uart-like byte transfer mode (btm). this mode allows sending and receiving individual bytes, but changes the behavior of the slcbt registers (now read/write registers) and locks the slcdlc to 1 byte data length. the slcbt value now becomes the bit time reference for the slic, where the so ftware sets the length of one bit time rather than the slic module itself. this is similar to an input capture/output compare (ic/oc) count in a timer module, where the count value represents the number of slic clock counts in one bit time. byte transfer mode assumes that the user has a very stable, precise oscillator, resonator, or clock reference input into the mcu and is therefore not appropriate for use with internal oscillators. there is no synchronization method available to the user in this mode and the user must tell the slic how many clock counts comprise a bit time. figure 14-25 , figure 14-26 , figure 14-27 , and figure 14-28 show calculations to determine the slcb t value for different settings. in the example in figure 14-25 , the user should write 0x16, as a write of 0x15 (decimal value of 21) would automatically re vert to 0x14, resulting in transmitted bit times that are 1.33 slic clock periods too short rather than 0.667 slic clock periods too long. the optimal choice, which gives the smallest resolution error, is the closest even number of slic clocks to the exact calculated slcbt value. there is a trade-off between maximum bit rate and resolution with the slic in btm mode. faster slic clock speeds improve resolution, but require higher numbers to be written to the slcbt registers for a give n desired bit rate. it is up to the user to determine what level of resolution is acceptable for the given application. table 14-7. maximum lin bit rates for high-speed operation due to digital receive filter slic clock (mhz) maximum lin bit rate for 1.5% slic accuracy (for master-slave communication (bits / second) digital rx filter not considered maximum lin bit rate with digital rx filter set to 4 (bits / second) maximum lin bit rate with digital rx filter set to 3 (bits / second) maximum lin bit rate with digital rx filter set to 2 (bits / second) maximum lin bit rate with digital rx filter set to 1 (bits / second) these prescalers not recommended for high-speed lin operation 8 120,000 125,000 166,667 250,000 500,000 6.4 96,000 100,000 133,333 200,000 400,000 4.8 72,000 75,000 100, 000 150,000 300,000 4 60,000 62,500 83,333 125,000 250,000 3.2 48,000 50,000 66,667 100,000 200,000 2.4 36,000 37,500 50,000 75,000 150,000 2 30,000 31,250 41,667 62,500 125,000 slave lin interface controller (slic) byte transfer mode operation mc68hc908ql family data sheet motorola slave lin interface controller (slic) 179 figure 14-25. slcbt value calculation example 1 figure 14-26. slcbt value calculation example 2 figure 14-27. slcbt value calculation example 3 4 cgmxclk period 21.33 slic clock periods 1 slic clock period 1 slic clock period x = 813.802 ns 1 bit 1 slic clock period = 813.802 ns 1 second 57,600 bits = 17.36111 ms 1 bit 4,915,200 cgmxclk periods 1 second x 17.36111 ms 1 bit desired bit rate: 57,600 bps external crystal frequency: 4.9152 mhz therefore, the closest sl cbt value would be 21 slic clocks (slcbt = 0x0015). since you can only use even values in slcbt, the closest acceptable value is 22 (0x0016). 4 cgmxclk period 42.67 slic clock periods 1 slic clock period 1 slic clock period x = 406.90 ns 1 bit 1 slic clock period = 406.90 ns 1 second 57,600 bits = 17.36111 ms 1 bit 9,830,400 cgmxclk periods 1 second x 17.36111 ms 1 bit desired bit rate: 57,600 bps external crystal frequency: 9.8304 mhz therefore, the closest sl cbt value would be 42 slic clocks (slcbt = 0x002a). 4 cgmxclk period 128 slic clock periods 1 slic clock period 1 slic clock period x = 500 ns 1 bit 1 slic clock period = 500 ns 1 second 15,625 bits = 64 ms 1 bit 8,000,000 cgmxclk periods 1 second x 64 ms 1 bit desired bit rate: 15,625 bps external crystal frequency: 8.000 mhz therefore, the closest slcbt value woul d be 128 slic clocks (slcbt = 0x0080). slave lin interface controller (slic) data sheet mc68hc908ql family 180 slave lin interface controller (slic) motorola figure 14-28. slcbt value calculation example 4 this resolution affects the sampling accu racy of the slic module on receiving bytes, but only as far as locating the sample point of each bit within a given byte. the best sample point of the bit may be off by as much as one slic clock period from the exact center of the bit, if the pr oper slcbt value for the desired bit rate is an odd number of slic clock periods. figure 14-29 shows an example of this error. in this example, the user has additionally chosen an incorrect value of 30 slic clocks for the length of one bit time, and a filter prescaler of 1. this makes little difference in the receive sampling of this particular bit, as the sample point is still within the bit and the digital filter will catch any noise pulses shorter than 16 filter clocks long.the ideal value of slcbt would be 35 slic clocks, but the closest available value is 34 , placing the sample point at 17 slic clocks into the bit. the error in the bit time value chosen by the user in the above example will grow throughout the byte, as the sample point for the next bit will be only 30 slic clock cycles later (1 full bit time at this bi t rate setting). the slic resynchronizes upon every falling edge received. in a 0x00 da ta byte, however, there are no falling edges after the beginning of the start bit. this means that the accumulated error of the sampling point over the data byte wi th these settings could be as high as 30 slic clock cycles (10 bits x {2 slic cl ocks due to user error + 1 slic clock resolution error}) placing it at the boundary between the last bit and the stop bit. this could result in missam pling and missing a framing error on the last bit on high speed communications when the slcbt count is relatively low. a properly chosen slcbt value would result in a maximum error of 10 slic clock counts over a given byte. this is less than one filter delay time, and will not cause missampling of any of the bits in that byte. at the falling edge of the next start bit, the slic will resynchronize and any accumulated sampling error returns to 0. the sampling error becomes even less significant at lo wer speeds, when higher values of slcbt are used to define a bit time, as the worst case bit time resolution error is still only one slic clock per bit (or maximum of 10 slic clocks per byte). 4 cgmxclk period 208.008 slic clock periods 1 slic clock period 1 slic clock period x = 500 ns 1 bit 1 slic clock period = 500 ns 1 second 9,615 bits = 104.004 ms 1 bit 8,000,000 cgmxclk periods 1 second x 104.004 ms 1 bit desired bit rate: 9.615 bps external crystal frequency: 8.000 mhz therefore, the closest slcbt value w ould be 42 slic clocks (slcbt = 0x00d0). slave lin interface controller (slic) byte transfer mode operation mc68hc908ql family data sheet motorola slave lin interface controller (slic) 181 figure 14-29. btm mode receive byte sampling example the error also comes into effect with tr ansmitted bit times. using the previous example with a slcbt value of 34, transm itted bits will appear as 34 slic clock periods long. this is one slic clock shor t of the proper length. depending on the frequency of the slic clock, one period of the slic clock might be a large or a small fraction of one ideal bit time. rais ing the frequency of the slic clock will reduce this error relative to the ideal bit time, improving the resolution of the slic clock relative to the bit rate of the bus. in any case, the error is still one slic clock cycle. raising the slic clock frequency, however, requires programming a higher value for slcbt to maintain the same target bit rate. smaller values of slcbt combined with higher values of the slic clock frequency (smaller clock period) will give faster bit rates, but the slic clock period becomes an increasingly significant portion of one bit time. since btm mode does not perform any sy nchronization and relies on the accuracy of the data provided by the user software to set its sample point and generate transmitted bits, the constraint on maximu m speeds is only limited to the limits imposed by the digital filter delay and the slic input clock. since the digital filter delay cannot be less than 16 slic clock cycles, the fastest possible pulse which filtered rx data filter clock unfiltered rx data 16 filter clocks ( 1 prescale) filter begins filter reaches 0x0 filter begins filter reaches 0xf and toggles filter output and toggles filter output slic clock ( 1 prescale) 15 slic clocks counting up 35 slic clocks counting down slic sample point (based on slcbt value) this example assumes a slcbt value of 30 (0x1e). ideal slic sample point (17 slic clocks) transmitted bits will be sent out as 30 slic clock cycles long. the proper closest slcbt setting would be 34 (0x22), which gives the ideal sample point of 17 slic clocks and transmitted bits are 34 slic clocks long. ( 1 prescale) 16 filter clocks ( 1 prescale) (1/2 of slcbt value) (actual filtered bit length) slave lin interface controller (slic) data sheet mc68hc908ql family 182 slave lin interface controller (slic) motorola would pass the filter is 16 clock period s at 8 mhz, or 500,000 bits/second. the values shown in table 14-8 are the same values shown in table 14-9 and indicate the absolute fastest bit rates which coul d just pass the minimum digital filter settings (prescaler = divide by 1) under perfect conditions. since perfect conditions are almost impossi ble to attain, more robust values must be chosen for bit rates. for reliable communication, it is best to ensure that a bit time is no smaller 2x?3x longer than the filter delay on the digital receive filter. this is true in lin or btm mode and ensures that valid data bits which have been shortened due to ground shift, asymmetrical rise and fall times, etc., are accepted by the filter without exception. this woul d translate to 2x to 3x reduction in the maximum speeds shown in table 14-8 . recommended maximum bit rates are shown in table 14-9 , and ensure that a single bit time is at least twice the length of one filter delay value. if system noise is not adequately filtered out it might be necessary to change the prescaler of the filter and lower the bit rate of the communication. if valid communications are being absorbed by the filter, corrective action must be taken to ensure that either the bit rate is reduced or whatever physical fault is causing bit times to shorten is corrected (ground offset, asymmetrical rise/fall times, insuffici ent physical layer supply voltage, etc.). table 14-8. digital receive filter absolute cutoff frequencies slic clock (mhz) maximum btm bit rate with digital rx filter set to 4 (bits / second) maximum btm bit rate with digital rx filter set to 3 (bits / second) maximum btm bit rate with digital rx filter set to 2 (bits / second) maximum btm bit rate with digital rx filter set to 1 (bits / second) 8 125,000 166,667 250,000 500,000 6.4 100,000 133,333 200,000 400,000 4.8 75,000 100,000 150,000 300,000 4 62,500 83,333 125,000 250,000 3.2 50,000 66,667 100,000 200,000 2.4 37,500 50,000 75,000 150,000 2 31,250 41,667 62,500 125,000 slave lin interface controller (slic) oscillator trimming with slic mc68hc908ql family data sheet motorola slave lin interface controller (slic) 183 14.19 oscillator trimming with slic the slcact bit can be used as an indicator of lin bus activity. slcact tells the user that the slic is currently processing a message header (therefore synchronizing to the bus) or processing a message frame (including checksum). therefore, at idle times between message frames or during a message frame which has been marked as a "don?t care" by wr iting the imsg bit, it is possible to trim the oscillator circuit of the mcu with no impact to the lin communications. it is important to note the exact mechanisms with which the slic sets and clears the slcact bit. any falling edge which successfully passes through the digital receive filter will cause the slcact bi t to become set. this might even include noise pulses, if they are of sufficient length to pass through the digital rx filter. although in these cases the slcact bit is becoming set on a noise spike, it is very probable that noise of this nature will c ause other system iss ues as well such as corruption of the message frame. the softw are can then further qualify if it is appropriate to trim the oscillator. the slcact bit will only be cleared by the slic upon successful completion of a normal lin message frame (see 14.6.3 slic status register description for more detail). this means that in some cases, if a message frame terminates with an error condition or some source other than those cited in the slcact bit description, the slcact might remain set during an otherwise idle bus time. the slcact will then clear upon the successful completion of the next lin message frame. these mechanisms might result in slcact being set when it is safe (from the slic module perspective) to trim the osci llator. however, the slcact bit will only be clear when the slic considers it safe to trim the oscillator. table 14-9. recommended maximum bit rates for btm operation due to digital filter slic clock (mhz) maximum btm bit rate with digital rx filter set to 4 (bits / second) maximum btm bit rate with digital rx filter set to 3 (bits / second) maximum btm bit rate with digital rx filter set to 2 (bits / second) maximum btm bit rate with digital rx filter set to 1 (bits / second) 8 62,500 83,333 125,000 250,000 6.4 50,000 66,667 100,000 200,000 4.8 37,500 50,000 75,000 150,000 4 31,250 41,667 62,500 125,000 3.2 25,000 33,333 50,000 100,000 2.4 18,750 25,000 37,500 125,000 2 15,625 20,833 31,250 62,500 slave lin interface controller (slic) data sheet mc68hc908ql family 184 slave lin interface controller (slic) motorola in a particular system, it might also be possible to improve the opportunities for trimming by utilizing system knowledge and use of the imsg bit. if a message id is known to be considered a "don?t care" by this particular node, it should be safe to trim the oscillator during that message frame (provided that it is safe for the application software as well). after the software has done an identifier lookup and determined that the id corresponds to a "don?t care" message, the software might choose to set the imsg bit. from that time, the application software should have at least one byte time of message traffic in which to trim the oscillator before that ignored message frame expires, regardless of the state of the slcact bit. if the length of that ignored message frame is known, that knowledge might also be utilized to extend the time of this oscillator trimming opportunity. now that the mechanisms for recognizing when the slic module indicates safe oscillator trimming opportuni ties are understood, it is important to understand how to derive the information needed to perform the trimming. the value in the slcbt register will indica te how many slic clock cycles comprise one bit time and for any given lin bus s peed, this will be a fixed value if the oscillator is running at its ideal frequency. it is possible to use this ideal value combined with the measured value in t he slcbt register to determine how to adjust the oscillator of the microcontroller. the actual oscillator trimming algorithm is very specific to each particular implementation, and applications might or might not require the oscillator even to be trimmed. the slic can maintain co mmunications even wi th input oscillator variation of 50% (with 4 mhz nominal, that means that any input clock into the slic from 2 mhz to 6 mhz will still gu arantee communications). since most motorola internal oscillators are at least within 25% of their nominal value, even when untrimmed, this means that trimming of the oscillator is not even required for lin communications. if the application can to lerate the range of frequencies which might appear within this manufacturing range, then it is not necessary ever to trim the oscillator. this can be a tremendous advantage to the customer, enabling migration to very low-cost rom device s which have no non-volatile memory in which to store the trim value. note: even though most internal oscillators are within 25% before trimming, they are stable at some frequency in that range, within at least 5% over the entire operating voltage and temperature range. the trimming operation simply eliminates the offset due to factory manuf acturing variations to re-center the base oscillator frequency to the nominal val ue. please refer to the electrical specifications for the oscillator for more sp ecific information, as exact specifications might differ from module to module. 14.20 digital receive filter the receiver section of the slic module includes a digital low-pass filter to remove narrow noise pulses from the incoming message. an outline of the digital filter is shown in figure 14-30 . slave lin interface controller (slic) digital receive filter mc68hc908ql family data sheet motorola slave lin interface controller (slic) 185 figure 14-30. slic module rx digital filter block diagram 14.20.1 operation the clock for the digital filter is provided by the slic interface clock. at each positive edge of the clock signal, the current state of the receiver input signal from the slcrx pad is sampled. the slcrx signal state is used to determine whether the counter should increment or decrement at the next positive edge of the clock signal. the counter will increment if the input data sample is high but decrement if the input sample is low. the counter will thus progr ess up towards ?15? if, on average, the slcrx signal remains high or progress down towards ?0? if, on average, the slcrx signal remains low. when the counter eventually reaches the val ue ?15?, the digital filter decides that the condition of the slcrx signal is at a stable logic level 1 and the data latch is set, causing the filtered rx data signal to become a logic level 1. furthermore, the counter is prevented from overflowing and can only be decremented from this state. alternatively, should the counter eventually reach the value ?0?, the digital filter decides that the condition of the slcrx signal is at a stable logic level 0 and the data latch is reset, causing the filtered rx data signal to become a logic level 0. furthermore, the counter is prevented from underflowing and can only be incremented from this state. the data latch will retain its value until the counter next reaches the opposite end point, signifying a definite transition of the slcrx signal. dq up/down out 4 edge & count comparator dq filtered rx data out slic clock rx data from slcrx pad input sync 4-bit up/down counter digital rx filter prescaler (rxfp[1:0]) slave lin interface controller (slic) data sheet mc68hc908ql family 186 slave lin interface controller (slic) motorola 14.20.2 performance the performance of the digital filter is best described in the time domain rather than the frequency domain. if the signal on the slcrx signal transitions, then there will be a delay before that transition appears at the filtered rx data output signal. this delay will be between 15 and 16 clock periods, depending on where the transition occurs with respect to the sampling points. this ?filter delay? is not an issue for slic operation, as there is no need for message arbitration. the effect of random noise on the slcrx signal depends on the characteristics of the noise itself. narrow noise pulses on the slcrx signal will be completely ignored if they are shorter than the filter delay. this provides a degree of low-pass filtering. figure 14-30 shows the configuration of the digital receive filter and the consequential effect on the filter delay. this filter delay value indicates that for a particular setup, only pulses of which are greater than the filter delay will pass the filter. for example, if the frequency of the slic clock (f slic ) is 3.2 mhz, then the period (t slic ) is of the slic clock is 313 ns. with the default receive filter prescaler setting of division by 3, the resulting maximum filter delay in the absence of noise will be 15.00 s. by simply changing the prescaler of the receive filter, the user can then select alternatively 5 s, 10 s, or 20 s as a minimum filter delay according to the systems requirements. if noise occurs during a symbol transition, the detection of that transition may be delayed by an amount equal to the length of the noise burst. this is just a reflection of the uncertainty of where the transit ion is truly occurri ng within the noise. note: the user must always account for the worst case bit timing of their lin bus when configuring the digital receive filter, espec ially if running at faster speeds. ground offset and other physical layer conditions can cause shortening of bits as seen at the digital receive pin, for example. if these shortened bit lengths are less than the filter delay, the bits will be interpreted by the filter as noise and will be blocked, even though the nominal bit timing might be greater than the filter delay. mc68hc908ql family data sheet motorola timer interface module (tim) 187 data sheet ? mc68hc908ql4 family section 15. timer inte rface module (tim) 15.1 introduction this section describes the timer interfac e module (tim). the tim is a two-channel timer that provides a timing reference with input capture, output compare, and pulse-width-modulation functions. figure 15-2 is a block diagram of the tim. 15.2 features features of the tim include the following: two input capture/output compare channels ? rising-edge, falling-edge, or any-edge input capture trigger ? set, clear, or toggle output compare action buffered and unbuffered pulse width modulation (pwm) signal generation programmable tim clock input ? 7-frequency internal bus clock prescaler selection ? external tim clock input free-running or modulo up-count operation toggle any channel pin on overflow tim counter stop and reset bits 15.3 pin name conventions the tim shares two input/output (i/o) pins with two port a i/o pins. the full names of the tim i/o pins are listed in table 15-1 . the generic pin name appear in the text that follows. table 15-1. pin name conventions tim generic pin names: tch0 tch1 tclk full tim pin names: ptb0/tch0 pta1/tch1 pta2/tclk timer interface module (tim) data sheet mc68hc908ql family 188 timer interface module (tim) motorola figure 15-1. block diagram highlighting tim block and pins rst , irq : pins have internal (about 30 k ? ) pull up pta0, pta1, pta3?pta5: high current sink and source capability pta0?pta5: pins have programmable keyboard interrupt and pull up adc pins only available on mc68hc908ql4 and mc68hc908ql2 pta0/ad0/kbi0 pta1/ad1/tch1/kbi1 pta2/irq /kbi2/tclk pta3/rst /kbi3 pta4/osc2/ad2/kbi4 pta5/osc1/ad3/kbi5 ptb0/tch0 ptb1 ptb2/ad4 ptb3/ad5 ptb4/slcrx ptb5/slctx ptb6 ptb7 power supply keyboard interrupt module clock generator (oscillator) system integration module single interrupt module break module power-on reset module 2-ch 16-bit timer module cop module monitor rom v dd v ss 128 bytes ram mc68hc908ql4 and mc68hc908ql3: 4096 bytes mc68hc908ql2: 2048 bytes user flash pta ddra ptb ddrb slave lin interface controller 6-channel 10-bit adc m68hc08 cpu timer interface module (tim) functional description mc68hc908ql family data sheet motorola timer interface module (tim) 189 15.4 functional description figure 15-2 shows the structure of the tim. the central component of the tim is the 16-bit tim counter that can operate as a free-running counter or a modulo up-counter. the tim counter provides t he timing reference for the input capture and output compare functions. the tim counter modulo registers, tmodh:tmodl, control the modulo value of the tim counter. software can read the tim counter value at any time wi thout affecting the counting sequence. the two tim channels are programmable inde pendently as input capture or output compare channels. figure 15-2. tim block diagram prescaler prescaler select 16-bit comparator ps2 ps1 ps0 16-bit comparator 16-bit latch tch0h:tch0l ms0a els0b els0a tof toie 16-bit comparator 16-bit latch tch1h:tch1l channel 0 channel 1 tmodh:tmodl trst tstop tov0 ch0ie ch0f els1b els1a tov1 ch1ie ch1max ch1f ch0max ms0b 16-bit counter internal bus ms1a internal bus clock tch1 tch0 interrupt logic port logic interrupt logic interrupt logic port logic pta2/irq /kbi2/tclk timer interface module (tim) data sheet mc68hc908ql family 190 timer interface module (tim) motorola addr. register name bit 7654321bit 0 $0020 tim status and control register (tsc) see page 197. read: tof toie tstop 00 ps2 ps1 ps0 write: 0 trst reset:00100000 $0021 tim counter register high (tcnth) see page 199. read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset:00000000 $0022 tim counter register low (tcntl) see page 199. read:bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 write: reset:00000000 $0023 tim counter modulo register high (tmodh) see page 199. read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset:11111111 $0024 tim counter modulo register low (tmodl) see page 199. read: bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 write: reset:11111111 $0025 tim channel 0 status and control register (tsc0) see page 200. read: ch0f ch0ie ms0b ms0a els0b els0a tov0 ch0max write: 0 reset:00000000 $0026 tim channel 0 register high (tch0h) see page 203. read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset: indeterminate after reset $0027 tim channel 0 register low (tch0l) see page 203. read: bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 write: reset: indeterminate after reset $0028 tim channel 1 status and control register (tsc1) see page 200. read: ch1f ch1ie 0 ms1a els1b els1a tov1 ch1max write: 0 reset:00000000 $0029 tim channel 1 register high (tch1h) see page 203. read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset: indeterminate after reset $002a tim channel 1 register low (tch1l) see page 203. read: bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 write: reset: indeterminate after reset = unimplemented figure 15-3. tim i/o register summary timer interface module (tim) functional description mc68hc908ql family data sheet motorola timer interface module (tim) 191 15.4.1 tim counter prescaler the tim clock source is one of the seven prescaler outputs or the tim clock pin, tclk. the prescaler generates seven clock rates from the internal bus clock. the prescaler select bits, ps[2:0], in the tim status and control register (tsc) select the tim clock source. 15.4.2 input capture with the input capture function, the tim ca n capture the time at which an external event occurs. when an active edge occurs on the pin of an input capture channel, the tim latches the contents of the tim counter into the tim channel registers, tchxh:tchxl. the polarity of the active edge is programmable. input captures can generate tim central processor unit (cpu) interrupt requests. 15.4.3 output compare with the output compare function, the tim can generate a periodic pulse with a programmable polarity, duration, and fr equency. when the counter reaches the value in the registers of an output compare channel, the tim can set, clear, or toggle the channel pin. output compares can generate tim cpu interrupt requests. 15.4.3.1 unbuffere d output compare any output compare channel can generate unbuffered output compare pulses as described in 15.4.3 output compare . the pulses are unbuffered because changing the output compare value requires writing the new value over the old value currently in the tim channel registers. an unsynchronized write to the tim ch annel registers to change an output compare value could cause incorrect operation for up to two counter overflow periods. for example, writing a new value before the counter reaches the old value but after the counter reaches the new value prevents any compare during that counter overflow period. also, using a tim overflow interrupt routine to write a new, smaller output compare value may cause the compare to be missed. the tim may pass the new value before it is written. use the following methods to synchroni ze unbuffered changes in the output compare value on channel x: when changing to a smaller value, enable channel x output compare interrupts and write the new value in the output compare interrupt routine. the output compare interrupt occurs at the end of the current output compare pulse. the interrupt routine has until the end of the counter overflow period to write the new value. when changing to a larger output compare value, enable tim overflow interrupts and write the new value in the tim overflow interrupt routine. the tim overflow interrupt occurs at the end of the current counter overflow timer interface module (tim) data sheet mc68hc908ql family 192 timer interface module (tim) motorola period. writing a larger value in an output compare interrupt routine (at the end of the current pulse) could cause two output compares to occur in the same counter overflow period. 15.4.3.2 buffered output compare channels 0 and 1 can be linked to form a buffered output compare channel whose output appears on the tch0 pin. the tim channel registers of the linked pair alternately control the output. setting the ms0b bit in tim channel 0 stat us and control register (tsc0) links channel 0 and channel 1. the output compare value in the tim channel 0 registers initially controls the output on the tch0 pin. writing to the tim channel 1 registers enables the tim channel 1 registers to synchronously control the output after the tim overflows. at each subsequent overflow, the tim channel registers (0 or 1) that control the output are the ones written to last. tsc0 controls and monitors the buffered output compare function, and tim channel 1 status and control register (tsc1) is unused. while the ms0b bit is set, the channel 1 pin, tch1, is available as a general-purpose i/o pin. note: in buffered output compare operation, do not write new output compare values to the currently active channel registers. user software should track the currently active channel to prevent writing a new val ue to the active channel. writing to the active channel registers is the same as generating unbuffered output compares. 15.4.4 pulse width modulation (pwm) by using the toggle-on-overflow feature with an output compare channel, the tim can generate a pwm signal. the value in the tim counter modulo registers determines the period of the pwm si gnal. the channel pin toggles when the counter reaches the value in the tim count er modulo registers. the time between overflows is the period of the pwm signal. as figure 15-4 shows, the output compare value in the tim channel registers determines the pulse width of the pw m signal. the time between overflow and output compare is the pulse width. program the tim to clear the channel pin on output compare if the state of the pwm pulse is logic 1. program the tim to set the pin if the state of the pwm pulse is logic 0. the value in the tim counter modulo registers and the selected prescaler output determines the frequency of the pwm output. the frequency of an 8-bit pwm signal is variable in 256 increments. writing $00ff (255) to the tim counter modulo registers produces a pwm period of 256 times the internal bus clock period if the prescaler select value is 000. see 15.9.1 tim status and control register . the value in the tim channel registers determines the pulse width of the pwm output. the pulse width of an 8-bit pwm signal is variable in 256 increments. writing $0080 (128) to the tim channel registers produces a duty cycle of 128/256 or 50%. timer interface module (tim) functional description mc68hc908ql family data sheet motorola timer interface module (tim) 193 figure 15-4. pwm period and pulse width 15.4.4.1 unbuffered pwm signal generation any output compare channel can generate unbuffered pwm pulses as described in 15.4.4 pulse width modulation (pwm) . the pulses are unbuffered because changing the pulse width requires writing t he new pulse width value over the old value currently in the tim channel registers. an unsynchronized write to the tim channel registers to change a pulse width value could cause incorrect operation for up to two pwm periods. for example, writing a new value before the counter re aches the old value but after the counter reaches the new value prevents any compar e during that pwm period. also, using a tim overflow interrupt routine to wr ite a new, smaller pulse width value may cause the compare to be missed. the ti m may pass the new value before it is written. use the following methods to synchronize unbuffered changes in the pwm pulse width on channel x: when changing to a shorter pulse wi dth, enable channel x output compare interrupts and write the new value in the output compare interrupt routine. the output compare interrupt occurs at the end of the current pulse. the interrupt routine has until the end of the pwm period to write the new value. when changing to a longer pulse width, enable tim overflow interrupts and write the new value in the tim overflow interrupt routine. the tim overflow interrupt occurs at the end of the current pwm period. writing a larger value in an output compare interrupt routine (at the end of the current pulse) could cause two output compares to occur in the same pwm period. note: in pwm signal generation, do not program the pwm channel to toggle on output compare. toggling on output compare prevents reliable 0% duty cycle generation and removes the ability of the channel to self-correct in the event of software error or noise. toggling on output compare also can cause incorrect pwm signal generation when changing the pwm pulse width to a new, much larger value. tchx period pulse width overflow overflow overflow output compare output compare output compare timer interface module (tim) data sheet mc68hc908ql family 194 timer interface module (tim) motorola 15.4.4.2 buffered pwm signal generation channels 0 and 1 can be linked to form a buffered pwm channel whose output appears on the tch0 pin. the tim channel registers of the linked pair alternately control the pulse width of the output. setting the ms0b bit in tim channel 0 stat us and control register (tsc0) links channel 0 and channel 1. the tim channel 0 registers initially control the pulse width on the tch0 pin. writing to the tim channel 1 registers enables the tim channel 1 registers to synchronously control the pulse width at the beginning of the next pwm period. at each subsequent overflow, the tim channel registers (0 or 1) that control the pulse width are the ones written to last. tsc0 controls and monitors the buffered pwm function, and tim channel 1 status and control register (tsc1) is unused. while the ms0b bit is set, t he channel 1 pin, tch1, is available as a general-purpose i/o pin. note: in buffered pwm signal generation, do not write new pulse width values to the currently active channel registers. user software should track the currently active channel to prevent writing a new value to the active channel. writing to the active channel registers is the same as generating unbuffered pwm signals. 15.4.4.3 pwm initialization to ensure correct operation when generating unbuffered or buffered pwm signals, use the following initialization procedure: 1. in the tim status and control register (tsc): a. stop the tim counter by setting the tim stop bit, tstop. b. reset the tim counter and prescaler by setting the tim reset bit, trst. 2. in the tim counter modulo registers (tmodh:tmodl), write the value for the required pwm period. 3. in the tim channel x registers (tchxh:tchxl), write the value for the required pulse width. 4. in tim channel x status and control register (tscx): a. write 0:1 (for unbuffered output compare or pwm signals) or 1:0 (for buffered output compare or pwm signals) to the mode select bits, msxb:msxa. see table 15-3 . b. write 1 to the toggle-on-overflow bit, tovx. c. write 1:0 (to clear output on compare) or 1:1 (to set output on compare) to the edge/level select bits, elsxb:elsxa. the output action on compare must force the output to the complement of the pulse width level. see table 15-3 . note: in pwm signal generation, do not program the pwm channel to toggle on output compare. toggling on output compare prevents reliable 0% duty cycle generation and removes the ability of the channel to self-correct in the event of software error timer interface module (tim) interrupts mc68hc908ql family data sheet motorola timer interface module (tim) 195 or noise. toggling on output compare can also cause incorrect pwm signal generation when changing the pwm pulse width to a new, much larger value. 5. in the tim status control register (tsc), clear the tim stop bit, tstop. setting ms0b links channels 0 and 1 and configures them for buffered pwm operation. the tim channel 0 registers (tch0h:tch0l) initially control the buffered pwm output. tim status control register 0 (tscr0) controls and monitors the pwm signal from the linked channels. ms0b takes priority over ms0a. clearing the toggle-on-overflow bit, tovx, inhibits output toggles on tim overflows. subsequent output compares try to force the output to a state it is already in and have no effect. the result is a 0% duty cycle output. setting the channel x maximum duty cycle bit (chxmax) and setting the tovx bit generates a 100% duty cycle output. see 15.9.4 tim channel status and control registers . 15.5 interrupts the following tim sources can generate interrupt requests: tim overflow flag (tof) ? the tof bit is set when the tim counter reaches the modulo value programmed in the tim counter modulo registers. the tim overflow interrupt enable bit, toie, enables tim overflow cpu interrupt requests. tof and toie are in the tim status and control register. tim channel flags (ch1f:ch0f) ? the chxf bit is set when an input capture or output compare occurs on channel x. channel x tim cpu interrupt requests are controlled by the channel x interrupt enable bit, chxie. channel x tim cpu interrupt requests are enabled when chxie =1. chxf and chxie are in the tim channel x status and control register. 15.6 wait mode the wait instruction puts the mcu in low power-consumption standby mode. the tim remains active after the execution of a wait instruction. in wait mode the tim registers are not accessible by the cpu. any enabled cpu interrupt request from the tim can bring the mcu out of wait mode. if tim functions are not required during wait mode, reduce power consumption by stopping the tim before executing the wait instruction. timer interface module (tim) data sheet mc68hc908ql family 196 timer interface module (tim) motorola 15.7 tim during break interrupts a break interrupt stops the tim counter. the system integration module (sim) contro ls whether status bits in other modules can be cleared during the break state. the bcfe bit in the break flag control register (bfcr) enables software to clear status bits during the break state. see 13.8.2 break flag control register . to allow software to clear status bits during a break interrupt, write a 1 to the bcfe bit. if a status bit is cleared during the break state, it remains cleared when the mcu exits the break state. to protect status bits during the break state, write a 0 to the bcfe bit. with bcfe at 0 (its default state), software can read and write i/o registers during the break state without affecting status bits. some status bits have a two-step read/write clearing procedure. if software does the first step on such a bit before the break, the bit cannot change during the break state as long as bcfe is at 0. after the break, doing the second step clears the status bit. 15.8 input/output signals port a shares three of its pins with the tim. two tim channel i/o pins are pta0/tch0 and pta1/tch1 and an alternate clock source is pta2/tclk. 15.8.1 tim clock pin (pta2/tclk) pta2/tclk is an external clock input that can be the clock source for the tim counter instead of the prescaled internal bus clock. select the pta2/tclk input by writing logic 1s to the three prescaler select bits, ps[2?0]. (see 15.9.1 tim status and control register .) when the pta2/tclk pin is the tim clock input, it is an input regardless of port pin initialization. 15.8.2 tim channel i/o pins (pta0/tch0 and pta1/tch1) each channel i/o pin is programmable inde pendently as an input capture pin or an output compare pin. pta0/tch0 can be configured as a buffered output compare or buffered pwm pin. timer interface module (tim) input/output registers mc68hc908ql family data sheet motorola timer interface module (tim) 197 15.9 input/output registers the following i/o registers control and monitor operation of the tim: tim status and control register (tsc) tim control registers (tcnth:tcntl) tim counter modulo registers (tmodh:tmodl) tim channel status and control registers (tsc0 and tsc1) tim channel registers (tch0h:tch0l and tch1h:tch1l) 15.9.1 tim status and control register the tim status and control register (tsc) does the following: enables tim overflow interrupts flags tim overflows stops the tim counter resets the tim counter prescales the tim counter clock tof ? tim overflow flag bit this read/write flag is set when the tim counter reaches the modulo value programmed in the tim counter modulo registers. clear tof by reading the tim status and control register when tof is set and then writing a 0 to tof. if another tim overflow occurs before the clearing sequence is complete, then writing 0 to tof has no effect. therefore, a tof interrupt request cannot be lost due to inadvertent clearing of tof. rese t clears the tof bit. writing a 1 to tof has no effect. 1 = tim counter has reached modulo value 0 = tim counter has not reached modulo value toie ? tim overflow interrupt enable bit this read/write bit enables tim overfl ow interrupts when the tof bit becomes set. reset clears the toie bit. 1 = tim overflow interrupts enabled 0 = tim overflow interrupts disabled address: $0020 bit 7654321bit 0 read: tof toie tstop 00 ps2 ps1 ps0 write: 0 trst reset:00100000 = unimplemented figure 15-5. tim status and control register (tsc) timer interface module (tim) data sheet mc68hc908ql family 198 timer interface module (tim) motorola tstop ? tim stop bit this read/write bit stops the tim counter. counting resumes when tstop is cleared. reset sets the tstop bit, sto pping the tim counter until software clears the tstop bit. 1 = tim counter stopped 0 = tim counter active note: do not set the tstop bit before entering wa it mode if the tim is required to exit wait mode. trst ? tim reset bit setting this write-only bit resets the tim counter and the tim prescaler. setting trst has no effect on any other registers. counting resumes from $0000. trst is cleared automatically after t he tim counter is reset and always reads as logic 0. reset clears the trst bit. 1 = prescaler and tim counter cleared 0 = no effect note: setting the tstop and trst bits simultaneous ly stops the tim counter at a value of $0000. ps[2:0] ? prescaler select bits these read/write bits select either the pta2/tclk pin or one of the seven prescaler outputs as the input to the tim counter as table 15-2 shows. reset clears the ps[2:0] bits. table 15-2. prescaler selection ps2 ps1 ps0 tim clock source 0 0 0 internal bus clock 1 0 0 1 internal bus clock 2 0 1 0 internal bus clock 4 0 1 1 internal bus clock 8 1 0 0 internal bus clock 16 1 0 1 internal bus clock 32 1 1 0 internal bus clock 64 111 pta2/tclk timer interface module (tim) input/output registers mc68hc908ql family data sheet motorola timer interface module (tim) 199 15.9.2 tim counter registers the two read-only tim counter registers contain the high and low bytes of the value in the tim counter. reading the high byte (tcnth) latches the contents of the low byte (tcntl) into a buffer. subsequent reads of tcnth do not affect the latched tcntl value until tcntl is read. reset clears the tim counter registers. setting the tim reset bit (trst) also clears the tim counter registers. note: if you read tcnth during a break interrupt, be sure to unlatch tcntl by reading tcntl before exiting the break interrupt. otherwise, tcntl retains the value latched during the break. 15.9.3 tim counter modulo registers the read/write tim modulo registers contain the modulo value for the tim counter. when the tim counter reaches the modulo value, the overflow flag (tof) becomes set, and the tim counter resumes counting from $0000 at the next timer clock. writing to the high byte (tmodh) inhibits the tof bit and overflow interrupts until the low byte (tmodl) is written. reset sets the tim counter modulo registers. note: reset the tim counter before writing to the tim counter modulo registers. address: $0021 tcnth bit 7654321bit 0 read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset:00000000 address: $0022 tcntl bit 7654321bit 0 read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset:00000000 = unimplemented figure 15-6. tim counter registers (tcnth:tcntl) address: $0023 tmodh bit 7654321bit 0 read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset:11111111 address: $0024 tmodl bit 7654321bit 0 read: bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 write: reset:11111111 figure 15-7. tim counter modulo registers (tmodh:tmodl) timer interface module (tim) data sheet mc68hc908ql family 200 timer interface module (tim) motorola 15.9.4 tim channel status and control registers each of the tim channel status and control registers does the following: flags input captures and output compares enables input capture and output compare interrupts selects input capture, output compare, or pwm operation selects high, low, or toggling output on output compare selects rising edge, falling edge, or any edge as the active input capture trigger selects output toggling on tim overflow selects 0% and 100% pwm duty cycle selects buffered or unbuffered output compare/pwm operation chxf ? channel x flag bit when channel x is an input capture channel, this read/write bit is set when an active edge occurs on the channel x pi n. when channel x is an output compare channel, chxf is set when the value in the tim counter registers matches the value in the tim channel x registers. clear chxf by reading the tim channel x status and control register with chxf set and then writing a 0 to chxf. if another interrupt request occurs before the clearing sequence is complete, then writing 0 to chxf has no effect. therefore, an interrupt request cannot be lost due to inadvertent clearing of chxf. reset clears the chxf bit. writing a 1 to chxf has no effect. 1 = input capture or output compare on channel x 0 = no input capture or output compare on channel x address: $0025 tsc0 bit 7654321bit 0 read: ch0f ch0ie ms0b ms0a els0b els0a tov0 ch0max write: 0 reset:00000000 address: $0028 tsc1 bit 7654321bit 0 read: ch1f ch1ie 0 ms1a els1b els1a tov1 ch1max write: 0 reset:00000000 = unimplemented figure 15-8. tim channel status and control registers (tsc0:tsc1) timer interface module (tim) input/output registers mc68hc908ql family data sheet motorola timer interface module (tim) 201 chxie ? channel x interrupt enable bit this read/write bit enables tim cpu interrupt service requests on channel x. reset clears the chxie bit. 1 = channel x cpu interrupt requests enabled 0 = channel x cpu interrupt requests disabled msxb ? mode select bit b this read/write bit selects buffered output compare/pwm operation. msxb exists only in the tim channel 0 status and control register. setting ms0b disables the channel 1 status and control register and reverts tch1 to general-purpose i/o. reset clears the msxb bit. 1 = buffered output compare/pwm operation enabled 0 = buffered output compare/pwm operation disabled msxa ? mode select bit a when elsxb:a 00, this read/write bit selects either input capture operation or unbuffered output compare/pwm operation. see table 15-3 . 1 = unbuffered output compare/pwm operation 0 = input capture operation when elsxb:a = 00, this read/write bit selects the initial output level of the tchx pin (see table 15-3 ). reset clears the msxa bit. 1 = initial output level low 0 = initial output level high note: before changing a channel function by wr iting to the msxb or msxa bit, set the tstop and trst bits in the tim status and control register (tsc). table 15-3. mode, edge, and level selection msxb msxa elsxb elsxa mode configuration x0 0 0 output preset pin under port control; initial output level high x1 0 0 pin under port control; initial output level low 00 0 1 input capture capture on rising edge only 0 0 1 0 capture on falling edge only 0 0 1 1 capture on rising or falling edge 01 0 0 output compare or pwm software compare only 0 1 0 1 toggle output on compare 0 1 1 0 clear output on compare 0 1 1 1 set output on compare 1 x 0 1 buffered output compare or buffered pwm toggle output on compare 1 x 1 0 clear output on compare 1 x 1 1 set output on compare timer interface module (tim) data sheet mc68hc908ql family 202 timer interface module (tim) motorola elsxb and elsxa ? edge/level select bits when channel x is an input capture channel, these read/write bits control the active edge-sensing logic on channel x. when channel x is an output compare channel, elsxb and elsxa control the channel x output behavior when an output compare occurs. when elsxb and elsxa are both clear, channel x is not connected to an i/o port, and pin tchx is available as a general-purpose i/o pin. table 15-3 shows how elsxb and elsxa work. reset clears the elsxb and elsxa bits. note: after initially enabling a tim channel r egister for input capture operation and selecting the edge sensitivity, clear chxf to ignore any erroneous edge detection flags. tovx ? toggle-on-overflow bit when channel x is an output compare channel, this read/write bit controls the behavior of the channel x output when the tim counter overflows. when channel x is an input capture channel, tovx has no effect. reset clears the tovx bit. 1 = channel x pin toggles on tim counter overflow. 0 = channel x pin does not toggl e on tim counter overflow. note: when tovx is set, a tim counter overfl ow takes precedence over a channel x output compare if both occur at the same time. chxmax ? channel x maximum duty cycle bit when the tovx bit is at 1, setting the chxmax bit forces the duty cycle of buffered and unbuffered pwm signals to 100%. as figure 15-9 shows, the chxmax bit takes effect in the cycle after it is set or cleared. the output stays at the 100% duty cycle level until the cycle after chxmax is cleared. figure 15-9. chxmax latency output overflow tchx period chxmax overflow overflow overflow overflow compare output compare output compare output compare timer interface module (tim) input/output registers mc68hc908ql family data sheet motorola timer interface module (tim) 203 15.9.5 tim channel registers these read/write registers contain the captured tim counter value of the input capture function or the output compare value of the output compare function. the state of the tim channel registers after reset is unknown. in input capture mode (msxb:msxa = 0:0), reading the high byte of the tim channel x registers (tchxh) inhibits input captures until the low byte (tchxl) is read. in output compare mode (msxb:msxa 0:0), writing to the high byte of the tim channel x registers (tchxh) inhibits output compares until the low byte (tchxl) is written. address: $0026 tch0h bit 7654321bit 0 read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset: indeterminate after reset address: $0027 tch0l bit 7654321bit 0 read: bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 write: reset: indeterminate after reset address: $0029 tch1h bit 7654321bit 0 read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset: indeterminate after reset address: $02a tch1l bit 7654321bit 0 read: bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 write: reset: indeterminate after reset figure 15-10. tim channel registers (tch0h/l:tch1h/l) timer interface module (tim) data sheet mc68hc908ql family 204 timer interface module (tim) motorola mc68hc908ql family data sheet motorola development support 205 data sheet ? mc68hc908ql4 family section 16. development support 16.1 introduction this section describes the break module, the monitor read-only memory (mon), and the monitor mode entry methods. 16.2 break module (brk) the break module can generate a break interrupt that stops normal program flow at a defined address to enter a background program. features include: accessible input/output (i/o) registers during the break interrupt central processor unit (cpu) generated break interrupts software-generated break interrupts computer operating properly (cop ) disabling during break interrupts 16.2.1 functional description when the internal address bus matches the value written in the break address registers, the break module is sues a breakpoint signal (bkpt ) to the system integration module (sim). the sim then c auses the cpu to load the instruction register with a software interrupt instruction (swi). the program counter vectors to $fffc and $fffd ($fefc and $fefd in monitor mode). the following events can cause a break interrupt to occur: a cpu generated address (the address in the program counter) matches the contents of the break address registers. software writes a 1 to the brka bit in the break status and control register. when a cpu generated address matches the contents of the break address registers, the break interrupt is generated. a return-from-interrupt instruction (rti) in the break routine ends the break interrupt and returns the microcontroller unit (mcu) to normal operation. figure 16-1 shows the structure of the break module. figure 16-2 provides a summary of the i/o registers. development support data sheet mc68hc908ql family 206 development support motorola figure 16-1. break module block diagram address bus[15:8] address bus[7:0] 8-bit comparator 8-bit comparator control break address register low break address register high address bus[15:0] bkpt (to sim) addr.register name bit 7654321bit 0 $fe00 break status register (bsr) see page 210. read: rrrrrr sbsw r write: note (1) reset: 0 $fe02 break auxiliary register (brkar) see page 209. read:0000000 bdcop write: reset:00000000 $fe03 break flag control register (bfcr) see page 210. read: bcferrrrrrr write: reset: 0 $fe09 break address high register (brkh) see page 209. read: bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 write: reset:00000000 $fe0a break address low register (brkl) see page 209. read: bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 write: reset:00000000 $fe0b break status and control register (brkscr) see page 208. read: brke brka 000000 write: reset:00000000 1. writing a 0 clears sbsw. = unimplemented r = reserved figure 16-2. break i/o register summary development support break module (brk) mc68hc908ql family data sheet motorola development support 207 when the internal address bus matches the value written in the break address registers or when software writes a 1 to the brka bit in the break status and control register, the cpu starts a break interrupt by: loading the instruction register with the swi instruction loading the program counter with $fffc and $fffd ($fefc and $fefd in monitor mode) the break interrupt timing is: when a break address is placed at the address of the instruction opcode, the instruction is not executed until after completion of the break interrupt routine. when a break address is placed at an address of an instruction operand, the instruction is executed before the break interrupt. when software writes a 1 to the brka bit, the break interrupt occurs just before the next instruction is executed. by updating a break address and clearing the brka bit in a break interrupt routine, a break interrupt can be generated continuously. caution: a break address should be placed at the address of the instruction opcode. when software does not change the break address and clears the brka bit in the first break interrupt routine, the next break interrupt will not be generated after exiting the interrupt routine even when the internal address bus matches the value written in the break address registers. 16.2.1.1 flag protection during break interrupts the system integration module (sim) contro ls whether or not module status bits can be cleared during the break state. the bcfe bit in the break flag control register (bfcr) enables software to clear status bits during the break state. see 13.8.2 break flag control register and the break interrupts subsection for each module. 16.2.1.2 tim during break interrupts a break interrupt stops the timer counter. 16.2.1.3 cop during break interrupts the cop is disabled during a break inte rrupt with monitor mode when bdcop bit is set in break auxiliary register (brkar). development support data sheet mc68hc908ql family 208 development support motorola 16.2.2 break module registers these registers control and monitor operation of the break module: break status and control register (brkscr) break address register high (brkh) break address register low (brkl) break status register (bsr) break flag control register (bfcr) 16.2.2.1 break status and control register the break status and control register (brkscr) contains break module enable and status bits. brke ? break enable bit this read/write bit enables breaks on break address register matches. clear brke by writing a 0 to bit 7. reset clears the brke bit. 1 = breaks enabled on 16-bit address match 0 = breaks disabled brka ? break active bit this read/write status and control bit is set when a break address match occurs. writing a 1 to brka generates a break interrupt. clear brka by writing a 0 to it before exiting the break routine. reset clears the brka bit. 1 = break address match 0 = no break address match address: $fe0b bit 7654321bit 0 read: brke brka 000000 write: reset:00000000 = unimplemented figure 16-3. break status and control register (brkscr) development support break module (brk) mc68hc908ql family data sheet motorola development support 209 16.2.2.2 break address registers the break address registers (brkh and brkl) contain the high and low bytes of the desired breakpoint address. reset clears the break address registers. 16.2.2.3 break auxiliary register the break auxiliary register (brkar) cont ains a bit that enables software to disable the cop while the mcu is in a stat e of break interrupt with monitor mode. bdcop ? break disable cop bit this read/write bit disables the cop during a break interrupt. reset clears the bdcop bit. 1 = cop disabled during break interrupt 0 = cop enabled during break interrupt address: $fe09 bit 7654321bit 0 read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset:00000000 figure 16-4. break address register high (brkh) address: $fe0a bit 7654321bit 0 read: bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 write: reset:00000000 figure 16-5. break address register low (brkl) address: $fe02 bit 7654321bit 0 read:0000000 bdcop write: reset:00000000 = unimplemented figure 16-6. break auxiliary register (brkar) development support data sheet mc68hc908ql family 210 development support motorola 16.2.2.4 break status register the break status register (bsr) contains a flag to indicate that a break caused an exit from wait mode. this register is only used in emulation mode. sbsw ? sim break stop/wait sbsw can be read within the break state sw i routine. the user can modify the return address on the stack by subtracting one from it. 1 = wait mode was exited by break interrupt 0 = wait mode was not exited by break interrupt 16.2.2.5 break flag control register the break control register (bfcr) contai ns a bit that enables software to clear status bits while the mcu is in a break state. bcfe ? break clear flag enable bit this read/write bit enables software to clear status bits by accessing status registers while the mcu is in a break state. to clear status bits during the break state, the bcfe bit must be set. 1 = status bits clearable during break 0 = status bits not clearable during break address: $fe00 bit 7654321bit 0 read: rrrrrr sbsw r write: note (1) reset: 0 r = reserved 1. writing a 0 clears sbsw. figure 16-7. break status register (bsr) address: $fe03 bit 7654321bit 0 read: bcferrrrrrr write: reset: 0 r = reserved figure 16-8. break flag control register (bfcr) development support monitor module (mon) mc68hc908ql family data sheet motorola development support 211 16.2.3 low-power modes the wait and stop instructions put the mcu in low power- consumption standby modes. if enabled, the break module will re main enabled in wait and stop modes. however, since the internal address bus does not increment in these modes, a break interrupt will never be triggered. 16.3 monitor module (mon) this subsection describes the monitor module (mon) and the monitor mode entry methods. the monitor allows debugging and programming of the microcontroller unit (mcu) through a single-wire interface with a host computer. monitor mode entry can be achieved without use of the higher test voltage, v tst , as long as vector addresses $fffe and $ffff are blank, thus reducing the hardware requirements for in-circuit programming. features include: normal user-mode pin functionality on most pins one pin dedicated to serial communication between mcu and host computer standard non-return-to-zero (nrz) communication with host computer execution of code in random-access memory (ram) or flash flash memory security feature (1) flash memory programming interface use of external 9.8304 mhz crystal or clock to generate internal frequency of 2.4576 mhz simple internal oscillator mode of oper ation (no external clock or high voltage) monitor mode entry without high voltage, v tst , if reset vector is blank ($fffe and $ffff contain $ff) standard monitor mode entry if high voltage is applied to irq 16.3.1 functional description figure 16-9 shows a simplified diagram of monitor mode entry. the monitor module receives and execut es commands from a host computer. figure 16-10 , figure 16-11 , and figure 16-12 show example circuits used to enter monitor mode and communicate with a host computer via a standard rs-232 interface. 1. no security feature is absolutely secure. howe ver, motorola?s strategy is to make reading or copying the flash difficult for unauthorized users. development support data sheet mc68hc908ql family 212 development support motorola figure 16-9. simplified monitor mode entry flowchart monitor mode entry por reset pta0 = 1, pta1 = 1, and pta4 = 0? irq = v tst ? yes no yes no forced monitor mode normal user mode normal monitor mode invalid user mode no no host sends 8 security bytes is reset por? yes yes yes no are all security bytes correct? no yes enable flash disable flash execute monitor code does reset occur? conditions from table 16-1 debugging and flash programming (if flash is enabled) pta0 = 1, reset vector blank? development support monitor module (mon) mc68hc908ql family data sheet motorola development support 213 simple monitor commands can access any memory address. in monitor mode, the mcu can execute code downloaded into ram by a host computer while most mcu pins retain normal operating mode functi ons. all communication between the host computer and the mcu is through the pta0 pin. a level-shifting and multiplexing interface is required between pta0 and th e host computer. pta0 is used in a wired-or configuration and requires a pullup resistor. the monitor code has been updated from pr evious versions of the monitor code to allow enabling the internal oscillator to g enerate the internal clock. this addition, which is enabled when irq is held low out of reset, is intended to support serial communication/programming at 9600 baud in monitor mode by using the internal oscillator, and the internal oscillator us er trim value osctrim (flash location $ffc0, if programmed) to generate the desired internal frequency (3.2 mhz). since this feature is enabled only when irq is held low out of reset, it cannot be used when the reset vector is programm ed (i.e., the value is not $ffff) because entry into monitor mode in this case requires v tst on irq . the irq pin must remain low during this monitor sessi on in order to maintain communication. table 16-1 shows the pin conditions for entering monitor mode. as specified in the table, monitor mode may be entered after a power-on reset (por) and will allow communication at 9600 baud provided one of the following sets of conditions is met: if $fffe and $ffff do not contain $ff (programmed state): ? the external clock is 9.8304 mhz ?irq = v tst if $fffe and $ffff contain $ff (erased state): ? the external clock is 9.8304 mhz ?irq = v dd (this can be implemented through the internal irq pullup) if $fffe and $ffff contain $ff (erased state): ?irq = v ss (internal oscillator is selected, no external clock required) the rising edge of the internal rst signal latches the monitor mode. once monitor mode is latched, the values on pta1 and pta4 pins can be changed. once out of reset, the mcu waits for t he host to send eight security bytes (see 16.3.2 security ). after the security bytes, the mcu sends a break signal (10 consecutive logic 0s) to the host, indi cating that it is ready to receive a command. development support data sheet mc68hc908ql family 214 development support motorola figure 16-10. monitor mode circuit (external clock, with high voltage) figure 16-11. forced monitor mode circuit (external clock, no high voltage) 9.8304 mhz clock + 10 k ? * v dd 10 k ? * rst (pta3) irq (pta2) pta0 osc1 (pta5) 8 7 db9 2 3 5 16 15 2 6 10 9 v dd max232 v+ v? 1 f + 1 2 3 4 5 6 74hc125 74hc125 10 k ? pta1 pta4 v ss 0.1 f v dd 1 k ? 9.1 v c1+ c1? 5 4 1 f c2+ c2? + 3 1 1 f + 1 f v dd + 1 f v tst * value not critical v dd v dd 10 k ? * rst (pta3) irq (pta2) pta0 osc1 (pta5) 8 7 db9 2 3 5 16 15 2 6 10 9 v dd 1 f max232 v+ v? v dd 1 f + 1 2 3 4 5 6 74hc125 74hc125 10 k ? n.c. pta1 n.c. pta4 v ss 0.1 f v dd 9.8304 mhz clock c1+ c1? 5 4 1 f c2+ c2? + 3 1 1 f + + + 1 f v dd 10 k ? * * value not critical n.c. development support monitor module (mon) mc68hc908ql family data sheet motorola development support 215 figure 16-12. forced monitor mode circuit (internal clock, no high voltage) 16.3.1.1 normal monitor mode rst and osc1 functions will be active on the pta3 and pta5 pins respectively as long as v tst is applied to the irq pin. if the irq pin is lowered (no longer v tst ) then the chip will still be operating in m onitor mode, but the pin functions will be determined by the settings in the configuration registers (see section 5. configuration register (config) ) when v tst was lowered. with v tst lowered, the bih and bil instructions will read the irq pin state only if irqen is set in the config2 register. if monitor mode was entered with v tst on irq , then the cop is disabled as long as v tst is applied to irq . rst (pta3) irq (pta2) pta0 10 k ? * osc1 (pta5) n.c. 8 7 db9 2 3 5 16 15 2 6 10 9 v dd 1 f max232 c1+ c1? v+ v? 5 4 1 f c2+ c2? v dd 1 f + 1 2 3 4 5 6 74hc125 74hc125 10 k ? n.c. pta1 n.c. pta4 v ss 0.1 f v dd + 3 1 1 f + + + 1 f v dd * value not critical n.c. data sheet mc68hc908ql family 216 development support motorola development support table 16-1. monitor mode signal requirements and options mode irq (pta2) rst (pta3) reset vector serial communication mode selection cop communication speed comments pta0 pta1 pta4 external clock bus frequency baud rate normal monitor v tst v dd x 1 1 0 disabled 9.8304 mhz 2.4576 mhz 9600 provide external clock at osc1. forced monitor v dd x $ffff (blank) 1 x x disabled 9.8304 mhz 2.4576 mhz 9600 provide external clock at osc1. v ss x $ffff (blank) 1 x x disabled x 3.2 mhz (trimmed) 9600 internal clock is active. user x x not $ffff xxxenabledxxx mon08 function [pin no.] v tst [6] rst [4] ? com [8] mod0 [12] mod1 [10] ? osc1 [13] ?? 1. pta0 must have a pullup resistor to v dd in monitor mode. 2. communication speed in the table is an example to obtain a baud rate of 9600. baud rate using external oscillator is bus fre quency / 256 and baud rate using internal oscillator is bus frequency / 333. 3. external clock is a 9.8304 mhz oscillator on osc1. 4. x = don?t care 5. mon08 pin refers to p&e microcomputer s ystems? mon08-cyclone 2 by 8-pin connector. nc 1 2 gnd nc 3 4 rst nc 5 6 irq nc 7 8 pta0 nc 9 10 pta4 nc 11 12 pta1 osc1 13 14 nc v dd 15 16 nc development support monitor module (mon) mc68hc908ql family data sheet motorola development support 217 16.3.1.2 forced monitor mode if entering monitor mode without high voltage on irq , then startup port pin requirements and conditions, (pta1/pta4) ar e not in effect. this is to reduce circuit requirements when performing in-circuit programming. note: if the reset vector is blank and monitor mode is entered, the chip will see an additional reset cycle after the initial power-on reset (por). once the reset vector has been programmed, the traditional method of applying a voltage, v tst , to irq must be used to enter monitor mode. if monitor mode was entered as a result of the reset vector being blank, the cop is always disabled regardless of the state of irq . if the voltage applied to the irq is less than v tst , the mcu will come out of reset in user mode. internal circuitry monitors the reset vector fetches and will assert an internal reset if it detects that the reset vectors are erased ($ff). when the mcu comes out of reset, it is forced into monitor mode without requiring high voltage on the irq pin. once out of reset, the monitor code is initially executing with the internal clock at its default frequency. if irq is held high, all pins will default to regular input port functions except for pta0 and pta5 which will operate as a serial communication port and osc1 input respectively (refer to figure 16-11 ). that will allow the clock to be driven from an external source through osc1 pin. if irq is held low, all pins will default to regular input port function except for pta0 which will operate as serial communication port. refer to figure 16-12 . regardless of the state of the irq pin, it will not function as a port input pin in monitor mode. bit 2 of the port a data register will always read 0. the bih and bil instructions will behave as if the irq pin is enabled, regardles s of the settings in the configuration register. see section 5. configuration register (config) . the cop module is disabled in forced monitor mode. any reset other than a power-on reset (por) will automatically force the mcu to come back to the forced monitor mode. 16.3.1.3 monitor vectors in monitor mode, the mcu uses different vectors for reset, swi (software interrupt), and break interrupt than those for user mode. the alternate vectors are in the $fe page instead of the $ff page and allow code execution from the internal monitor firmware instead of user code. note: exiting monitor mode after it has been initiated by having a blank reset vector requires a power-on reset (por). pulling rst (when rst pin available) low will not exit monitor mode in this situation. development support data sheet mc68hc908ql family 218 development support motorola table 16-2 summarizes the differences between user mode and monitor mode regarding vectors. 16.3.1.4 data format communication with the monitor rom is in standard non-return-to-zero (nrz) mark/space data format. transmit and receive baud rates must be identical. figure 16-13. monitor data format 16.3.1.5 break signal a start bit (logic 0) followed by nine logi c 0 bits is a break signal. when the monitor receives a break signal, it drives the pt a0 pin high for the duration of two bits and then echoes back the break signal. figure 16-14. break transaction 16.3.1.6 baud rate the monitor communication baud rate is controlled by the frequency of the external or internal oscillator and the state of the appropriate pins as shown in table 16-1 . table 16-1 also lists the bus frequencies to achieve standard baud rates. the effective baud rate is the bus frequenc y divided by 256 when us ing an external oscillator. when using the inte rnal oscillator in forced monitor mode, the effective baud rate is the bus frequency divided by 335. table 16-2. mode difference modes functions reset vector high reset vector low break vector high break vector low swi vector high swi vector low user $fffe $ffff $fffc $fffd $fffc $fffd monitor $fefe $feff $fefc $fefd $fefc $fefd bit 5 start bit bit 1 next stop bit start bit bit 2 bit 3 bit 4 bit 7 bit 0 bit 6 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 missing stop bit approximately 2 bits delay before zero echo development support monitor module (mon) mc68hc908ql family data sheet motorola development support 219 16.3.1.7 commands the monitor rom firmware uses these commands: read (read memory) write (write memory) iread (indexed read) iwrite (indexed write) readsp (read stack pointer) run (run user program) the monitor rom firmware echoes each re ceived byte back to the pta0 pin for error checking. an 11-bit delay at the end of each command allows the host to send a break character to cancel the command. a delay of two bit times occurs before each echo and before read, iread, or readsp data is returned. the data returned by a read command appears after the echo of the last byte of the command. note: wait one bit time after each ec ho before sending the next byte. figure 16-15. read transaction figure 16-16. write transaction read read echo from host address high address high address low address low data return 13, 2 11 4 4 notes: 2 = data return delay, approximately 2 bit times 3 = cancel command delay, 11 bit times 4 = wait 1 bit time before sending next byte. 44 1 = echo delay, approximately 2 bit times write write echo from host address high address high address low address low data data notes: 2 = cancel command delay, 11 bit times 3 = wait 1 bit time before sending next byte. 11 3 11 3 3 32, 3 1 = echo delay, approximately 2 bit times development support data sheet mc68hc908ql family 220 development support motorola a brief description of each m onitor mode command is given in table 16-3 through table 16-8 . table 16-3. read (read memory) command description read byte from memory operand 2-byte address in high-byte:low-byte order data returned returns contents of specified address opcode $4a command sequence table 16-4. write (write memory) command description write byte to memory operand 2-byte address in high-byte:low-byte order; low byte followed by data byte data returned none opcode $49 command sequence table 16-5. iread (indexed read) command description read next 2 bytes in memory from last address accessed operand 2-byte address in high byte:low byte order data returned returns contents of next two addresses opcode $1a command sequence read read echo sent to monitor address high address high address low data return address low write write echo from host address high address high address low address low data data iread iread echo from host data return data development support monitor module (mon) mc68hc908ql family data sheet motorola development support 221 a sequence of iread or iwrite comman ds can access a block of memory sequentially over the full 64-kbyte memory map. table 16-6. iwrite (indexed write) command description write to last address accessed + 1 operand single data byte data returned none opcode $19 command sequence table 16-7. readsp (read stack pointer) command description reads stack pointer operand none data returned returns incremented stack pointer value (sp + 1) in high-byte:low-byte order opcode $0c command sequence table 16-8. run (run user program) command description executes pulh and rti instructions operand none data returned none opcode $28 command sequence iwrite iwrite echo from host data data readsp readsp echo from host sp return sp high low run run echo from host development support data sheet mc68hc908ql family 222 development support motorola the mcu executes the swi and pshh instructions when it enters monitor mode. the run command tells the mcu to execute the pulh and rti instructions. before sending the run command, the host can modify the stacked cpu registers to prepare to run the host program. the readsp command returns the incremented stack pointer value, sp + 1. the high and low bytes of the program counter are at addresses sp + 5 and sp + 6. figure 16-17. stack pointer at monitor mode entry 16.3.2 security a security feature discourages unauthori zed reading of flash locations while in monitor mode. the host can bypass the se curity feature at monitor mode entry by sending eight security bytes that matc h the bytes at locations $fff6?$fffd. locations $fff6?$fffd contain user-defined data. note: do not leave locations $fff6?$fffd blank. for security reasons, program locations $fff6?$fffd even if they are not used for vectors. during monitor mode entry, the mcu waits after the power-on reset for the host to send the eight security bytes on pin pta0 . if the received bytes match those at locations $fff6?$fffd, the host bypasses the security feature and can read all flash locations and execute code from fl ash. security remains bypassed until a power-on reset occurs. if the reset was not a power-on reset, security remains bypassed and security code entry is not required. see figure 16-18 . upon power-on reset, if the received bytes of the security code do not match the data at locations $fff6?$fffd, the host fails to bypass the security feature. the mcu remains in monitor mode, but reading a flash location returns an invalid value and trying to execute code from flash causes an illegal address reset. after receiving the eight security bytes from the host, the mcu transmits a break character, signifying that it is ready to receive a command. note: the mcu does not transmit a break character until after the host sends the eight security bytes. condition code register accumulator low byte of index register high byte of program counter low byte of program counter sp + 1 sp + 2 sp + 3 sp + 4 sp + 5 sp sp + 6 high byte of index register sp + 7 development support monitor module (mon) mc68hc908ql family data sheet motorola development support 223 figure 16-18. monitor mode entry timing to determine whether the security code entered is correct, check to see if bit 6 of ram address $80 is set. if it is, then the correct security code has been entered and flash can be accessed. if the security sequence fails, the devic e should be reset by a power-on reset and brought up in monitor mode to attempt another entry. after failing the security sequence, the flash module can also be mass erased by executing an erase routine that was downloaded into internal ram. the mass erase operation clears the security code locations so that all eight security bytes become $ff (blank). byte 1 byte 1 echo byte 2 byte 2 echo byte 8 byte 8 echo command command echo pa0 rst v dd 4096 + 32 busclkx4 cycles 5 1 4 1 1 2 1 break notes: 2 = data return delay, approximately 2 bit times 4 = wait 1 bit time before sending next byte 4 from host from mcu 1 = echo delay, approximately 2 bit times 5 = wait until the monitor rom runs development support data sheet mc68hc908ql family 224 development support motorola mc68hc908ql family data sheet motorola electrical specifications 225 data sheet ? mc68hc908ql4 family section 17. electrical specifications 17.1 introduction this section contains electric al and timing specifications. 17.2 absolute maximum ratings maximum ratings are the extreme limits to which the microcontroller unit (mcu) can be exposed without permanently damaging it. note: this device is not guaranteed to operate properly at the maximum ratings. refer to 17.5 5-v dc electrical characteristics and 17.9 3.3-v dc electrical characteristics for guaranteed operating conditions. note: this device contains circuitry to pr otect the inputs against damage due to high static voltages or electric fields; however , it is advised that normal precautions be taken to avoid application of any volta ge higher than maximum-rated voltages to this high-impedance circuit. for proper operation, it is recommended that v in and v out be constrained to the range v ss (v in or v out ) v dd . reliability of operation is enhanced if unused inputs are connected to an appropriate logic voltage level (for example, either v ss or v dd .) characteristic (1) 1. voltages references to v ss . symbol value unit supply voltage v dd ?0.3 to +6.0 v input voltage v in v ss ?0.3 to v dd +0.3 v mode entry voltage, irq pin v tst v ss ?0.3 to +9.1 v maximum current per pin excluding pta0?pta5, v dd , and v ss i15ma maximum current for pins pta0?pta5 i pta0? i pta5 25 ma storage temperature t stg ?55 to +150 c maximum current out of v ss i mvss 100 ma maximum current into v dd i mvdd 100 ma electrical specifications data sheet mc68hc908ql family 226 electrical specifications motorola 17.3 functional o perating range 17.4 thermal characteristics characteristic symbol value unit temp. code operating temperature range (t l to t h )t a ? 40 to +125 ? 40 to +105 ? 40 to +85 c m v c operating voltage range (1) (v ddmin to v ddmax ) 1. v dd must be above v tripr upon power on. v dd 2.2 to 3.6 v characteristic symbol value unit thermal resistance 16-pin pdip 16-pin soic 16-pin tssop ja 76 90 133 c/w i/o pin power dissipation p i/o user determined w power dissipation (1) 1. power dissipation is a function of temperature. p d p d = (i dd x v dd ) + p i/o = k/(t j + 273c) w constant (2) 2. k constant unique to the device. k can be determined for a known t a and measured p d. with this value of k, p d and t j can be determined for any value of t a . k p d x (t a + 273c) + p d 2 x ja w/c average junction temperature t j t a + (p d x ja ) c maximum junction temperature t jm 150 c electrical specifications 5-v dc electrical characteristics mc68hc908ql family data sheet motorola electrical specifications 227 17.5 5-v dc electri cal characteristics characteristic (1) symbol min typ (2) max unit output high voltage i load = ?2.0 ma, all i/o pins i load = ?10.0 ma, all i/o pins i load = ?15.0 ma, pta0, pta1, pta3?pta5 only v oh v dd ?0.4 v dd ?1.5 v dd ?0.8 ? ? ? ? ? ? v maximum combined i oh (all i/o pins) i oht ??50ma output low voltage i load = 1.6 ma, all i/o pins i load = 10.0 ma, all i/o pins i load = 15.0 ma, pta0, pta1, pta3?pta5 only v ol ? ? ? ? ? ? 0.4 1.5 0.8 v maximum combined i ol (all i/o pins) i ohl ??50ma input high voltage pta0?pta5, ptb0?ptb7 v ih 0.7 x v dd ? v dd v input low voltage pta0?pta5, ptb0?ptb7 v il v ss ? 0.3 x v dd v input hysteresis v hys 0.06 x v dd ??v dc injection current, all ports i inj ?2 ? +2 ma total dc current injection (sum of all i/o) i injtot ?25 ? +25 ma digital i/o ports hi-z leakage current typical at 25 wc i il ?10 ? ? 0.1 +10 ? a digital input only ports leakage current (pa2/irq /kbi2 ) i in ?1 ? +1 a capacitance ports (as input) ports (as input) c in c out ? ? ? ? 12 8 pf por rearm voltage (3) v por 0?100mv por rise time ramp rate (4) r por 0.035 ? ? v/ms monitor mode entry voltage v tst v dd + 2.5 ?9.1v pullup resistors (5) pta0?pta5, ptb0?ptb7 r pu 16 26 36 k ? low-voltage inhibit reset, trip falling voltage v tripf 3.90 4.20 4.50 v low-voltage inhibit reset, trip rising voltage v tripr 4.00 4.30 4.60 v low-voltage inhibit reset/recover hysteresis v hys ? 100 ? mv 1. v dd = 3.0 to 5.5 vdc, v ss = 0 vdc, t a = t l to t h , unless otherwise noted. 2. typical values reflect average measurement s at midpoint of voltage range, 25c only. 3. maximum is highest vo ltage that por is guaranteed. 4. if minimum v dd is not reached before the internal por reset is re leased, lvi will hold the part in reset until minimum v dd is reached. 5. r pu1 and r pu2 are measured at v dd = 5.0 v. electrical specifications data sheet mc68hc908ql family 228 electrical specifications motorola 17.6 control timing figure 17-1. rst and irq timing characteristic (1) symbol min max unit internal operating frequency f op (f bus ) ?2mhz internal clock period (1/f op )t cyc 500 ? ns rst input pulse width low t rl 175 ? ns irq interrupt pulse width low (edge-triggered) t ilih 125 ? ns irq interrupt pulse period t ilil note (2) ? t cyc 1. v ss = 0 vdc; timing shown with respect to 20% v dd and 70% v dd unless otherwise noted. 2. the minimum period is the number of cycles it take s to execute the interrupt service routine plus 1 t cyc . rst irq t rl t ilih t ilil electrical specifications typical 5-v output drive characteristics mc68hc908ql family data sheet motorola electrical specifications 229 17.7 typical 5-v output drive characteristics figure 17-2. typical 5-volt output high voltage versus output high current (25c) figure 17-3. typical 5-volt output low voltage versus output low current (25c) 0.0 0.5 1.0 1.5 2.0 -35 -30 -25 -20 -15 -10 -5 0 ioh (ma) vdd-voh (v) 5v pta 5v ptb 0.0 0.5 1.0 1.5 2.0 0 5 10 15 20 25 30 35 iol (ma) vol (v) 5v pta 5v ptb electrical specifications data sheet mc68hc908ql family 230 electrical specifications motorola 17.8 5-v oscillat or characteristics figure 17-4. rc versus frequency (5 volts @ 25c) characteristic symbol min typ max unit internal oscillator frequency (1) f intclk ?25.6?mhz crystal frequency, xtalclk (1) f oscxclk 8?32mhz external rc oscillator frequency, rcclk (1) f rcclk 2?12mhz external clock reference frequency (1) (2) f oscxclk dc ? 32 mhz crystal load capacitance (3) c l ?20?pf crystal fixed capacitance (2) c 1 ? 2 x c l ?? crystal tuning capacitance (2) c 2 ? 2 x c l ?? feedback bias resistor r b ?10?m ? rc oscillator external resistor r ext see figure 17-4 ? 1. bus frequency, f op , is oscillator frequency divided by 4. 2. no more than 10% duty cycle deviation from 50%. 3. consult crystal vendor data sheet. 0 0 1020304050 14 12 10 8 6 4 2 resistor, r ext (k ? ) rc frequency, f rcclk (mhz) r ext osc1 v dd mcu 5 v @ 25c electrical specifications 3.3-v dc electrical characteristics mc68hc908ql family data sheet motorola electrical specifications 231 17.9 3.3-v dc electr ical characteristics characteristic (1) symbol min typ (2) max unit output high voltage i load = ?0.6 ma, all i/o pins i load = ?4.0 ma, all i/o pins i load = ?10.0 ma, pta0, pta1, pta3?pta5 only v oh v dd ?0.3 v dd ?1.0 v dd ?0.8 ? ? ? ? ? ? v maximum combined i oh (all i/o pins) i oht ??50ma output low voltage i load = 0.5 ma, all i/o pins i load = 6.0 ma, all i/o pins i load = 10.0 ma, pta0, pta1, pta3?pta5 only v ol ? ? ? ? ? ? 0.3 1.0 0.8 v maximum combined i ol (all i/o pins) i ohl ??50ma input high voltage pta0?pta5, ptb0?ptb7 v ih 0.7 x v dd ? v dd v input low voltage pta0?pta5, ptb0?ptb7 v il v ss ? 0.3 x v dd v input hysteresis v hys 0.06 x v dd ?? v dc injection current, all ports i inj ?2 ? +2 ma total dc current injection (sum of all i/o) i injtot ?25 ? +25 ma digital i/o ports hi-z leakage current typical at 25c i il ?10 ? ? 0.5 +10 ? a digital input only ports leakage current (pa2/irq/kbi2 ) i in ?1 ? +1 a capacitance ports (as input) ports (as input) c in c out ? ? ? ? 12 8 pf por rearm voltage (3) v por 0 ? 100 mv por rise time ramp rate (4) r por 0.035 ? ? v/ms monitor mode entry voltage v tst v dd + 2.5 ? v dd + 4.0 v pullup resistors (5) pta0?pta5, ptb0?ptb7 r pu 16 26 36 k ? low-voltage inhibit reset, trip falling voltage v tripf 2.65 2.8 3.0 v low-voltage inhibit reset, trip rising voltage v tripr 2.75 2.9 3.10 v low-voltage inhibit reset/recover hysteresis v hys ?60?mv 1. v dd = 3.0 to 3.6 vdc, v ss = 0 vdc, t a = t l to t h , unless otherwise noted. 2. typical values reflect average measurement s at midpoint of voltage range, 25c only. 3. maximum is highest vo ltage that por is guaranteed. 4. if minimum v dd is not reached before the internal por reset is released, lvi will hold the part in reset until minimum v dd is reached. 5. r pu1 and r pu2 are measured at v dd = 3.0 v electrical specifications data sheet mc68hc908ql family 232 electrical specifications motorola 17.10 typical 3.3-v output drive characteristics figure 17-5. typical 3.3-volt output high voltage versus output high current (25c) figure 17-6. typical 3.3-volt output low voltage versus output low current (25c) 0.0 0.5 1.0 1.5 -20 -15 -10 -5 0 ioh (ma) vdd-voh (v) 3v pta 3v ptb 0.0 0.5 1.0 1.5 0 5 10 15 20 iol (ma) vol (v) 3v pta 3v ptb electrical specifications 3.3-v control timing mc68hc908ql family data sheet motorola electrical specifications 233 17.11 3.3-v control timing 17.12 3.3-v oscillat or characteristics figure 17-7. rc versus frequency (3 volts @ 25c) characteristic (1) symbol min max unit internal operating frequency (2) f op ?4mhz rst input pulse width low (3) t irl 1.5 ? s 1. v dd = 3.0 to 3.6 vdc, v ss = 0 vdc, t a = t l to t h ; timing shown with respect to 20% v dd and 70% v dd , unless otherwise noted. 2. some modules may require a minimum frequency greater than dc for proper operation; s ee appropriate table for this information. 3. minimum pulse width reset is guaranteed to be recognized. it is possible for a smaller pulse width to cause a reset. characteristic symbol min typ max unit internal oscillator frequency (1) f intclk ?12.8?mhz crystal frequency, xtalclk (1) f oscxclk 8?16mhz external rc oscillator frequency, rcclk (1) f rcclk 2?12mhz external clock reference frequency (1) (2) f oscxclk dc ? 16 mhz crystal load capacitance (3) c l ?20?pf crystal fixed capacitance (2) c 1 ? 2 x c l ?? crystal tuning capacitance (2) c 2 ? 2 x c l ?? feedback bias resistor r b ?10? m ? rc oscillator external resistor r ext see figure 17-7 ? 1. bus frequency, f op , is oscillator frequency divided by 4. 2. no more than 10% duty cycle deviation from 50% 3. consult crystal vendor data sheet 0 0 1020304050 14 12 10 8 6 4 2 resistor, r ext (k ? ) rc frequency, f rcclk (mhz) r ext osc1 v dd mcu 3 v @ 25c electrical specifications data sheet mc68hc908ql family 234 electrical specifications motorola 17.13 supply current characteristics characteristic (1) voltage bus freq. (mhz) symbol typ max unit run mode v dd supply current (2) 5.0 3.3 4 4 ri dd 4.5 2.7 ? ? ma wait mode v dd supply current (3) 5.0 3.3 4 4 wi dd 1.7 1.0 ? ? ma stop mode v dd supply current (4) ?40 to 85 c ?40 to 105 c ?40 to 125 c 25 c 25 c with auto wake-up enabled incremental current with lvi enabled at 25 c 5.0 si dd 0.10 0.22 0.34 6.50 5.70 125 ? ? ? ? ? ? a a a na a a ?40 to 85 c ?40 to 105 c ?40 to 125 c 25 c 25 c with auto wake-up enabled incremental current with lvi enabled at 25 c 3.3 0.10 0.14 0.18 4.60 1.30 102 ? ? ? ? ? ? a a a na a a 1. v dd = 3.3 to 5.5 vdc, v ss = 0 vdc, t a = t l to t h , unless otherwise noted. 2. run (operating) i dd measured using external square wave clock source. all inputs 0.2 v from rail. no dc loads. less than 100 pf on all outputs. all ports configured as inputs. measured with all modules enabled. 3. wait (operating) i dd measured using external square wave clock source. all inputs 0.2 v from rail. no dc loads. less than 100 pf on all outputs. all ports configured as inputs. measured with all modules enabled. 4. stop i dd measured with all ports driven 0.2 v or less from rail. no dc loads. on the 8-pin versions, port b is configured as inputs with pullups enabled. electrical specifications supply current characteristics mc68hc908ql family data sheet motorola electrical specifications 235 figure 17-8. typical 5-volt run current versus bus frequency (25c) figure 17-9. typical 3.3-volt run current versus bus frequency (25c) 0 2 4 6 8 10 12 14 01234567 bus frequency (mhz) idd (ma) crystal w/o adc crystal w/ adc internal osc w/o adc internal osc w/ adc 0 1 2 3 4 012345 bus frequency (mhz) idd (ma) crystal w/o adc crystal w/ adc internal osc w/o adc internal osc w/ adc electrical specifications data sheet mc68hc908ql family 236 electrical specifications motorola 17.14 analog-to-digital converter characteristics characteristic symbol min max unit comments supply voltage v ddad 3.0 (v dd min) 5.5 (v dd max) v? input voltages v adin v ss v dd v? resolution b ad 88bits ? absolute accuracy a ad 0.5 1.5 lsb includes quantization adc internal clock f adic 0.5 1.048 mhz t adic = 1/f adic , tested only at 1 mhz conversion range r ad v ss v dd v? power-up time t adpu 16 ? t adic cycles t adic = 1/f adic conversion time t adc 16 17 t adic cycles t adic = 1/f adic sample time (1) t ads 5? t adic cycles t adic = 1/f adic zero input reading (2) z adi 00 01 hex v in = v ss full-scale reading (3) f adi fe ff hex v in = v dd input capacitance c adi ? 8 pf not tested input leakage (3) ? i inadc ? ? 1 a? 1. source impedances greater than 10 k ? adversely affect internal rc charging time during input sampling. 2. zero-input/full-scale reading requires sufficien t decoupling measures for accurate conversions. 3. the external system error caused by input leakage current is approximately equal to the product of r source and input current. electrical specifications timer interface module characteristics mc68hc908ql family data sheet motorola electrical specifications 237 17.15 timer interface mo dule characteristics figure 17-10. input capture timing characteristic symbol min max unit timer input capture pulse width t th, t tl 2? t cyc timer input capture period t tltl note (1) ? t cyc timer input clock pulse width t tcl , t tch t cyc + 5 ?ns 1. the minimum period is the number of cycles it take s to execute the interrupt service routine plus 1 t cyc . input capture rising edge input capture falling edge input capture both edges t th t tl t tltl t tltl t tltl t tl t th tclk t tcl t tch electrical specifications data sheet mc68hc908ql family 238 electrical specifications motorola 17.16 memory characteristics characteristic symbol min typ max unit ram data retention voltage v rdr 1.3 ? ? v flash program bus clock frequency ? 1 ? ? mhz flash read bus clock frequency f read (1) 0?8 mhz flash page erase time <1 k cycles >1 k cycles t erase 0.9 3.6 1 4 1.1 5.5 ms flash mass erase time t merase 4??ms flash pgm/erase to hven setup time t nvs 10 ? ? s flash high-voltage hold time t nvh 5?? s flash high-voltage hold time (mass erase) t nvhl 100 ? ? s flash program hold time t pgs 5?? s flash program time t prog 30 ? 40 s flash return to read time t rcv (2) 1?? s flash cumulative program hv period t hv (3) ?? 4ms flash endurance (4) ? 10 k 100 k ? cycles flash data retention time (5) ? 15 100 ? years 1. f read is defined as the frequency range for which the flash memory can be read. 2. t rcv is defined as the time it needs before the flash can be read after turning off the high voltage charge pump, by clearing hven to 0. 3. t hv is defined as the cumulative high voltage programming time to the same row before next erase. t hv must satisfy this condition: t nvs + t nvh + t pgs + (t prog x 32) t hv maximum. 4. typical endurance was evaluated for this product family. for additional information on how motorola defines. typical endurance , please refer to engineering bulletin eb619. 5. typical data retention values are based on intrinsic capability of the technology measured at high temp erature and de-rated to 25c using the arrhenius equation. for additional information on how motorola defines typical data retention , please refer to engineering bulletin eb618. mc68hc908ql family data sheet motorola ordering information and mechanical specifications 239 data sheet ? mc68hc908ql4 family section 18. ordering informatio n and mechanical specifications 18.1 introduction this section provides ordering information for the mc68hc908ql4, mc68hc908ql3, and mc68hc908ql2 al ong with the dimensions for: 16-pin plastic dual in-line package (pdip 16-pin small outline integrated circuit (soic) package 16-pin thin shrink small outline package (tssop) the following figures show the latest pac kage drawings at the time of this publication. to make sure that you have the latest package specifications, contact your local motorola sales office. 18.2 mc order numbers figure 18-1. device numbering system table 18-1. mc order numbers mc order number adc flash memory package mc68hc908ql4 yes 4096 bytes 16-pins pdip, soic, and tssop mc68hc908ql3 no 4096 bytes mc68hc908ql2 yes 2048 bytes temperature and package designators: c = ?40c to +85c v = ?40c to +105c (available for v dd = 5 v only) m = ?40c to +125c (available for v dd = 5 v only) p = plastic dual in-line package (pdip) dw = small outline integrated circuit package (soic) dt = thin shrink small outline package (tssop) m c 6 8 h c 9 0 8 q l x x x x family package designator temperature range ordering information and mechanical specifications data sheet mc68hc908ql family 240 ordering information and mechanical specifications motorola 18.3 16-pin plastic dual in-line pa ckage (case #648d) 18.4 16-pin small outline in tegrated circui t package (case #751g) dim min max min max millimeters inches a 0.740 0.760 18.80 19.30 b 0.245 0.260 6.23 6.60 c 0.145 0.175 3.69 4.44 d 0.015 0.021 0.39 0.53 f 0.050 0.070 1.27 1.77 g 0.100 bsc 2.54 bsc h 0.050 bsc 1.27 bsc j 0.008 0.015 0.21 0.38 k 0.120 0.140 3.05 3.55 l 0.295 0.305 7.50 7.74 m 0 10 0 10 s 0.015 0.035 0.39 0.88 notes: 1. dimensioning a nd tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. 3. dimension l to center of leads when formed parallel. 4. dimensions a and b do not include mold protrusion. 5. mold flash or protrusions shall not exceed 0.25 (0.010). 6. rounded corners optional. ordering information and mechanical specifications 16-pin thin shrink small outline package (case #948f) mc68hc908ql family data sheet motorola ordering information and mechanical specifications 241 18.5 16-pin thin shrink smal l outline package (case #948f) dim min max min max inches millimeters a 4.90 5.10 0.193 0.200 b 4.30 4.50 0.169 0.177 c --- 1.20 --- 0.047 d 0.05 0.15 0.002 0.006 f 0.50 0.75 0.020 0.030 g 0.65 bsc 0.026 bsc h 0.18 0.28 0.007 0.011 j 0.09 0.20 0.004 0.008 j1 0.09 0.16 0.004 0.006 k 0.19 0.30 0.007 0.012 k1 0.19 0.25 0.007 0.010 l 6.40 bsc 0.252 bsc m 0 8 0 8 notes: 1. dimensioning a nd tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a does not include mold flash. protrusion s or gate burrs. mold flash or gate burrs shall not exceed 0.15 (0.006) per side. 4. dimension b does not include interlead flash or protrusion. interlead flash or protrusion shall not exceed 0.25 (0.010) per side. 5. dimension k does not include dambar protrusion. allowable dambar protrusion shall be 0.08 (0.003) total in excess of the k dimension at maximum material condition. 6. terminal numbers are shown for reference only. 7. dimension a and b are to be determined at datum plane -w-. section n-n seating plane ident. pin 1 1 8 16 9 detail e j j1 b c d a k k1 h g detail e f m l 2x l/2 -u- s u 0.15 (0.006) t s u 0.15 (0.006) t s u m 0.10 (0.004) v s t 0.10 (0.004) -t- -v- -w- 0.25 (0.010) 16x ref k n n ordering information and mechanical specifications data sheet mc68hc908ql family 242 ordering information and mechanical specifications motorola how to reach us: usa/europe/locations not listed: motorola literature distribution p.o. box 5405 denver, colorado 80217 1-800-521-6274 or 480-768-2130 japan: motorola japan ltd. sps, technical information center 3-20-1, minami-azabu, minato-ku tokyo 106-8573, japan 81-3-3440-3569 asia/pacific: motorola semiconductors h.k. ltd. silicon harbour centre 2 dai king street tai po industrial estate tai po, n.t., hong kong 852-26668334 home page: http://motorola.com/semiconductors mc68hc908ql4/d rev. 0 9/2003 information in this document is provided solely to enable system and software implementers to use motorola products. there are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. motorola reserves the right to make changes without further notice to any products herein. motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability , including without limitation consequential or incidental damages. ?typical? parameters that may be provided in motorola data sheets and/or specifications can and do vary in differen t applications and actual performance may vary over time. all operating parameters, including ?typicals?, must be validated for each customer application by customer?s technical experts. motorola does not convey any license under its patent rights nor the rights of others. motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the motorola product could create a situation where personal injury or death may occur. should buyer purchase or use motorola products for any such unintended or unauthorized application, buyer shall indemnify and hold motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that motorola was negligent regarding the design or manufacture of the part. motorola and the stylized m logo are registered in the us patent and trademark office. all other product or service names are the property of their respective owners. motorola, inc. is an equal opportunity/affirmative action employer. ? motorola inc. 2003 |
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